Datasheet LT8601 (Analog Devices) - 10

LT8601
PIN FUNCTIONS BIAS (Pin 10):
Power to the Internal Regulator. Connect
PVIN1, PVIN2 (Pins 37, 14):
Input Supply Voltage to High to an output ≥ 3.2V when available. Decouple to ground Voltage Channels 1 and 2, respectively. These pins are with a low ESR capacitor. independent and can be powered from different sources
BST1, BST2 (Pins 4, 5):
Boost Voltage for High Voltage if necessary. Bypass each input with a low ESR capacitor Channels. The Boost Voltage provides a drive voltage to the adjacent GND pin. higher than PVIN to the gate of the NMOS top switch.
PVIN3 (Pin 17):
Input Supply Voltage to Low Voltage
CPOR (Pin 31):
Power-On Reset Timer. Connect a capaci- Channel 3. This pin is typically connected to one of the tor from this pin to ground to program the power-on reset high voltage converter outputs and should be locally timer. CPOR has a 2μA (typical) pull-up current. bypassed with a low ESR capacitor.
EN/UVLO (Pin 22):
Enable/Undervoltage Lockout Input.
RST (Pin 32):
Power-On Reset Output. CMOS output with The LT8601 is in low power shutdown when this pin is weak pull-up, this pin is held low until the POR times out. ≤ 0.4V. A precision threshold at 1.20V (rising) enables
RT (Pin 29):
Frequency Programming Resistor. Connect the switching regulator’s output switching stages. This a resistor from this pin to ground to set the internal oscil- allows the EN/UVLO pin to be used as an input undervolt- age lockout by connecting to a resistor divider between lator frequency. VIN and GND. When the EN/UVLO voltage is between 0.4V
RUN3 (Pin 18):
Run Input for the Low Voltage Converter. and 1.2V, the LT8601 input current will depend on the Channel 3 is enabled when the voltage on this pin exceeds mode selected, the VIN voltage, and the EN/UVLO voltage. 0.72V (typical). Connect this pin to VIN if the UVLO function is not needed.
SW1 (Pin 3):
Channel 1 Switch Node. This is the output
FB1, FB2 (Pins 26, 25):
Feedback Input Pins for the High of the internal power switches for channel 1. Voltage Converters. The converters regulate the corre- sponding feedback pin to the lesser of 1V or the voltage
SW2 (Pins 6, 7):
Channel 2 Switch Node. This is the out- on the associated TRKSS pin. put of the internal power switches for channel 2. These pins must be connected together.
FB3 (Pin 24):
Feedback Input Pin for the Low Voltage Converter. The converter regulates the corresponding
SW3 (Pin 15):
Channel 3 Switch Node. This is the output feedback pin to 800mV. of the internal power switches for channel 3.
GND (Pins 2, 8, 9, 13, 16, 27, 30, 34, 35, 38, 40, 41): SYNC (Pin 33):
Clock Synchronization and Mode Select Ground. These pins must be soldered to PCB ground. Input. Connect this pin to ground to enable low ripple The exposed pad must also be soldered to PCB ground. Burst Mode operation. Connect this pin to INTVCC to enable pulse skip operation. Apply a digital clock input to
INTVCC (Pin 28):
Internal Regulator Bypass. Do not load the INTV synchronize the LT8601 switching frequency to a refer- CC pin with external circuitry. INTVCC is 3.1V when BIAS < 3.1V, 3.4V when BIAS > 3.4V, and approxi- ence clock. When an external clock is applied, the LT8601 mately equal to BIAS when BIAS is between 3.1V and will operate in pulse-skipping mode. 3.4V. Decouple to ground with a low ESR, 4.7μF capacitor.
TRKSS1, TRKSS2 (Pins 21, 20):
Track/Soft-Start Inputs
PG1, PG2 (Pins 1, 11):
Power Good Indicators for Channels for the High Voltage Converters. When this pin is below 1 and 2. Open-drain logic output pulls down until the corre- 1V, the converter regulates the FB pin to the TRKSS volt- sponding FB pin rises above 0.92V but remains below 1.08V. age instead of the internal reference. The TRKSS pin has a 2.4μA (typical) pull-up current.
PG3 (Pin 12):
Power Good Indicator for Channel 3. Open- drain logic output pulls down until the corresponding FB
VIN (Pin 23):
Input Supply Voltage to Internal Functions. pin rises above 0.736V but remains below 0.864V. This pin is independent from any PVIN pin and can be powered from different sources if necessary. V
POREN (Pin 39):
Power-On Reset Enable. This is a logic IN must be above 3V for the part to operate. input that starts the ramp on the POR timing capacitor. Rev. B 10 For more information www.analog.com Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Pin Configuration Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Typical Applications Package Description Revision History Typical Application Related Parts