Datasheet MASTERGAN2 (STMicroelectronics) - 5
| Hersteller | STMicroelectronics |
| Beschreibung | High power density 600V Half bridge driver with two enhancement mode GaN HEMT |
| Seiten / Seite | 29 / 5 — MASTERGAN2. Recommended operating conditions. 3.2 |
| Dateiformat / Größe | PDF / 1.6 Mb |
| Dokumentensprache | Englisch |
MASTERGAN2. Recommended operating conditions. 3.2
Modelllinie für dieses Datenblatt
Textversion des Dokuments
link to page 5 link to page 5 link to page 5 link to page 5 link to page 5
MASTERGAN2 Recommended operating conditions 3.2 Recommended operating conditions Table 3. Recommended operating conditions (Each voltage referred to GND unless otherwise specified) Symbol Parameter Note Min Max Unit
VS High voltage bus 0 520 V VCC Supply voltage 4.75 9.5 V 4.75 6.5 V PVCC-PGND PVCC to PGND low side supply voltage (1) Best performance 5 6.5 V PVCC Low-side driver supply voltage 3 8.5 V VCC-PVCC VCC to PVCC pin voltage -3 3 V PGND Low-side driver ground(1) -2 2 V DT Suggested minimum deadtime 5 ns TIN_MIN Minimum duration of input pulse to obtain undistorted output pulse 120 ns 4.4 6.5 V VBO BOOT to OUTb pin voltage (2) Best performance 5 6.5 V BOOT BOOT to GND voltage 0 (3) 530 V Vi Logic inputs voltage range 0 20 V TJ Junction temperature -40 125 °C 1. PGND internally connected to SENSE 2. OUTb internally connected to OUT 3. 5 V is recommended during high-hide turn-on
3.3 Thermal data Table 4. Thermal data Symbol Parameter Value Unit
Rth(J-CB)_LS Thermal resistance Low side junction to SENSE exposed pad, typical 1.9 °C/W Rth(J-CB)_HS Thermal resistance High side junction to OUT exposed pad, typical 2.8 °C/W Rth(J-A) Thermal resistance junction-to-ambient (1) 17.8 °C/W 1. The junction to ambient thermal resistance is obtained simulating the device mounted on a 2s2p (4 layer) FR4 board as JESD51-5,7 with 6 thermal vias for each exposed pad. Power dissipation uniformly distributed over the two GaN transistors.
DS13597
-
Rev 1 page 5/29
Document Outline Features Application Description 1 Block diagram 2 Pin description and connection diagram 2.1 Pin list 3 Electrical Data 3.1 Absolute maximum ratings 3.2 Recommended operating conditions 3.3 Thermal data 4 Electrical characteristics 4.1 Driver 4.2 GaN power transistor 5 Device characterization values 6 Functional description 6.1 Logic inputs 6.2 Bootstrap structure 6.3 VCC supply pins and UVLO function 6.4 VBO UVLO protection 6.5 Thermal shutdown 7 Typical application diagrams 8 Package information 8.1 QFN 9 x 9 x 1 mm, 31 leads, pitch 0.6 mm package information 9 Suggested footprint 10 Ordering information Revision history Contents List of tables List of figures
MASTERGAN2 Recommended operating conditions 3.2 Recommended operating conditions Table 3. Recommended operating conditions (Each voltage referred to GND unless otherwise specified) Symbol Parameter Note Min Max Unit
VS High voltage bus 0 520 V VCC Supply voltage 4.75 9.5 V 4.75 6.5 V PVCC-PGND PVCC to PGND low side supply voltage (1) Best performance 5 6.5 V PVCC Low-side driver supply voltage 3 8.5 V VCC-PVCC VCC to PVCC pin voltage -3 3 V PGND Low-side driver ground(1) -2 2 V DT Suggested minimum deadtime 5 ns TIN_MIN Minimum duration of input pulse to obtain undistorted output pulse 120 ns 4.4 6.5 V VBO BOOT to OUTb pin voltage (2) Best performance 5 6.5 V BOOT BOOT to GND voltage 0 (3) 530 V Vi Logic inputs voltage range 0 20 V TJ Junction temperature -40 125 °C 1. PGND internally connected to SENSE 2. OUTb internally connected to OUT 3. 5 V is recommended during high-hide turn-on
3.3 Thermal data Table 4. Thermal data Symbol Parameter Value Unit
Rth(J-CB)_LS Thermal resistance Low side junction to SENSE exposed pad, typical 1.9 °C/W Rth(J-CB)_HS Thermal resistance High side junction to OUT exposed pad, typical 2.8 °C/W Rth(J-A) Thermal resistance junction-to-ambient (1) 17.8 °C/W 1. The junction to ambient thermal resistance is obtained simulating the device mounted on a 2s2p (4 layer) FR4 board as JESD51-5,7 with 6 thermal vias for each exposed pad. Power dissipation uniformly distributed over the two GaN transistors.
DS13597
-
Rev 1 page 5/29
Document Outline Features Application Description 1 Block diagram 2 Pin description and connection diagram 2.1 Pin list 3 Electrical Data 3.1 Absolute maximum ratings 3.2 Recommended operating conditions 3.3 Thermal data 4 Electrical characteristics 4.1 Driver 4.2 GaN power transistor 5 Device characterization values 6 Functional description 6.1 Logic inputs 6.2 Bootstrap structure 6.3 VCC supply pins and UVLO function 6.4 VBO UVLO protection 6.5 Thermal shutdown 7 Typical application diagrams 8 Package information 8.1 QFN 9 x 9 x 1 mm, 31 leads, pitch 0.6 mm package information 9 Suggested footprint 10 Ordering information Revision history Contents List of tables List of figures