Datasheet 2ED24427N01F (Infineon) - 9

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2ED24427N01F 10 A dual-channel low-side gate driver IC
V*µs ratings: this factor must be respected, in bipolar drive application (like the one shown in Figure 5) a maximum of up to twice that parameter is still acceptable for most manufacturers, this factor then must be chosen accordingly to the following formula: 𝑉𝑝𝑟𝑖𝑚∗𝛿 𝑉 ∗ µ𝑠 𝑟𝑎𝑡𝑖𝑛𝑔 (∗ 2) ≥ (1) 𝑓𝑠𝑤 where Vprim is the voltage applied to the primary, δ is the duty cycle and fsw the switching frequency of the application. N, turns ratio: usually 1:1, in some cases 1:2 or 1:1:1 (dual driver) this determines the voltage ratio between primary and secondary. Lp, primary inductance: this value determines the magnetizing inductance as follows: 𝐿𝑚 = 𝐿𝑝 ∗ 𝐾 (2) where K is the coupling factor between primary and secondary windings. LLK, leakage inductance: this parameter, usually indicated at primary, is equal to: 𝐿𝐿𝐾 = 𝐿𝑝 ∗ (1 − 𝐾) (3) The higher Lm is, the lower is the magnetizing current flowing into the transformer and consequent power losses into the driver. On the other hand the lower LLK is, the lower and shorter will be the ringing of the secondary LC network created by LLK, and Ciss of the fet, damped by Rgss and much lower overshot will appear on the Vgs across the Fet during transition. Then a too high Lm requires a very good mechanical construction of the gate transformer to achieve high K and consequent low LLK. In a gate driver application running in the range of 50 kHz-200 kHz and using the 2ED24427N01F, a good choice is usually a Lm between 300 µH and 2 mH and a LLK < 1µH. This translate for the formula (2) and (3) above in a coupling factor K between 0.9940 and 0.9995 For good operation and to reduce unneeded power losses into the 2ED24427N01F driver, the magnetizing current has to be kept ILM < 0.5 A, from this then derives a minimum Lm to be calculated as follows: 𝑉𝑔 𝛿 𝐿𝑚𝑚𝑖𝑛 = ∗ (4) 0.5 𝑓𝑠𝑤 Where Vg is the gate driving voltage of the Fet Figure 6 shows a good design waveform obtained with the following parameters: Vg =+/-15 V, Lm = 400 µH, LLK = 0.4 µH, N = 1, fsw = 100 kHz, CissFET = 10 nF, Rg,ps = 3Ω, Rg,ss = 4Ω, and Cdec = 1 µF Cdec is the AC coupling capacitor needed to reset the driver transformer flux, its value has to be calculated in a way that the voltage across it can be considered constant during normal operation. The higher the fsw the smaller will be Cdec. A ceramic capacitor is normally used. Datasheet 9 of 21 V 2.0 www.infineon.com/gdLowSide 2019-11-10