Datasheet CS5171, CS5172, CS5173, CS5174 (ON Semiconductor) - 10

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CS5171, CS5172, CS5173, CS5174 APPLICATIONS INFORMATION THEORY OF OPERATION
The oscillator is trimmed to guarantee an 18% frequency
Current Mode Control
accuracy. The output of the oscillator turns on the power switch at a frequency of 280 kHz (CS5171/2) or 560 kHz VCC (CS5173/4), as shown in Figure 27. The power switch is Oscillator turned off by the output of the PWM Comparator. S V − Q L A TTL−compatible sync input at the SS pin is capable of C + R syncing up to 1.8 times the base oscillator frequency. As Power Switch D1 PWM Com- VSW shown in Figure 28, in order to sync to a higher frequency, parator In Out CO a positive transition turns on the power switch before the RLOAD Driver output of the oscillator goes high, thereby resetting the X5 SUMMER oscillator. The sync operation allows multiple power 63 mW Slope Compensation supplies to operate at the same frequency. A sustained logic low at the SS pin will shut down the IC and reduce the supply current.
Figure 27. Current Mode Control Scheme
An additional feature includes frequency shift to 20% of The CS517x family incorporates a current mode control the nominal frequency when either the NFB or FB pins scheme, in which the PWM ramp signal is derived from the trigger the threshold. During power up, overload, or short power switch current. This ramp signal is compared to the circuit conditions, the minimum switch on−time is limited output of the error amplifier to control the on−time of the by the PWM comparator minimum pulse width. Extra power switch. The oscillator is used as a fixed−frequency switch off−time reduces the minimum duty cycle to protect clock to ensure a constant operational frequency. The external components and the IC itself. resulting control scheme features several advantages over As previously mentioned, this block also produces a ramp conventional voltage mode control. First, derived directly for the slope compensation to improve regulator stability. from the inductor, the ramp signal responds immediately to line voltage changes. This eliminates the delay caused by the
Error Amplifier
output filter and error amplifier, which is commonly found in voltage mode controllers. The second benefit comes from 200 k 2.0 V inherent pulse−by−pulse current limiting by merely 250 k NFB + clamping the peak switching current. Finally, since current
CS5172/4
mode commands an output current rather than voltage, the − filter offers only a single pole to the feedback loop. This negative error−amp VC allows both a simpler compensation and a higher C1 120 pF 1M gain−bandwidth over a comparable voltage mode circuit. W + 0.01 mF Voltage 1.276 V Clamp Without discrediting its apparent merits, current mode R1 − FB 5 kW control comes with its own peculiar problems, mainly,
CS5171/3
positive error−amp subharmonic oscillation at duty cycles over 50%. The CS517x family solves this problem by adopting a slope
Figure 29. Error Amplifier Equivalent Circuit
compensation scheme in which a fixed ramp generated by For CS5172/4, the NFB pin is internally referenced to the oscillator is added to the current ramp. A proper slope −2.5 V with approximately a 250 kW input impedance. For rate is provided to improve circuit stability without CS5171/3, the FB pin is directly connected to the inverting sacrificing the advantages of current mode control. input of the positive error amplifier, whose non−inverting
Oscillator and Shutdown
input is fed by the 1.276 V reference. Both amplifiers are transconductance amplifiers with a high output impedance of approximately 1 MW, as shown in Figure 29. The VC pin Sync is connected to the output of the error amplifiers and is Current internally clamped between 0.5 V and 1.7 V. A typical Ramp connection at the V V C pin includes a capacitor in series with SW a resistor to ground, forming a pole/zero for loop compensation.
Figure 28. Timing Diagram of Sync and Shutdown
An external shunt can be connected between the VC pin and ground to reduce its clamp voltage. Consequently, the current limit of the internal power transistor current is reduced from its nominal value.
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