Preliminary Datasheet QPC1252Q (Qorvo) - 9
| Hersteller | Qorvo |
| Beschreibung | Broadband High Linearity DSDA e-Call Antenna Routing Switch |
| Seiten / Seite | 17 / 9 — PRELIMINARY. QPC1252Q. BROADBAND HIGH LINEARITY DSDA e-CALL ANTENNA … |
| Dateiformat / Größe | PDF / 976 Kb |
| Dokumentensprache | Englisch |
PRELIMINARY. QPC1252Q. BROADBAND HIGH LINEARITY DSDA e-CALL ANTENNA ROUTING SWITCH. Reg28 (0x1C) ─ PM_TRIG. Bit(s). Field Name
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PRELIMINARY QPC1252Q BROADBAND HIGH LINEARITY DSDA e-CALL ANTENNA ROUTING SWITCH Reg28 (0x1C) ─ PM_TRIG Bit(s) Field Name Description Reset B/G Trig R/W
0: Normal Operation (ACTIVE) 7 PWR_MODE[7] 1 B/G No R/W 1: Low Power - Antenna in isolation 0: Normal Operation (ACTIVE) 1: INITIALIZATION STATE - Reset all registers to default settings 6 PWR_STATE[6] 0 B/G No R/W Note: This bit always reads 0. Writing a 1 to this bit forces a reset. Setting bit TriggerMask[N] disables Trigger[N] TriggerMask[N] updates before Trigger[N] is processed Note: When Trigger[N] is disabled, writing to a register associated 5:3 TriggerMask[2:0] 0b000 No No R/W with Trigger[N] sends data directly to that register. If a register is associated with multiple triggers, then all associated triggers must be disabled to allow direct writes to the associated register. Setting bit Trigger[N] loads Trigger[N]'s associated registers Note: When Trigger[N] is enabled, writing to a register associated 2:0 Trigger[2:0] 0b000 B/G No R/W with Trigger[N] sends data to that register's shadow. Setting the Trigger[N] bit loads data from shadow. All triggers are processed immediately and simultaneously and then cleared. Trigger[0], [1], and [2] will always read as 0.
Reg29 (0x1D) ─ PRODUCT_ID Bit(s) Field Name Description Reset B/G Trig R/W
Lower eight bits of Product Number Note: These are read-only registers. However, as part of the special 7:0 PROD_ID[7:0] 0x4C No No R programming sequence for writing USID, a write command sequence is performed on one or both registers, but does not update them. See MIPI 6.6.2 for details.
Reg30 (0x1E) ─ MANUFACTURER_ID Bit(s) Field Name Description Reset B/G Trig R/W
Lower eight bits of MIPI Manufacturer ID Note: These are read-only registers. However, as part of the special 7:0 MFG_ID[7:0] 0xC6 No No R programming sequence for writing USID, a write command sequence is performed on one or both registers, but does not update them. See MIPI 6.6.2 for details. QPC1252Q Preliminary DS RevA | Subject to change without notice 9 of 17
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0: Normal Operation (ACTIVE) 7 PWR_MODE[7] 1 B/G No R/W 1: Low Power - Antenna in isolation 0: Normal Operation (ACTIVE) 1: INITIALIZATION STATE - Reset all registers to default settings 6 PWR_STATE[6] 0 B/G No R/W Note: This bit always reads 0. Writing a 1 to this bit forces a reset. Setting bit TriggerMask[N] disables Trigger[N] TriggerMask[N] updates before Trigger[N] is processed Note: When Trigger[N] is disabled, writing to a register associated 5:3 TriggerMask[2:0] 0b000 No No R/W with Trigger[N] sends data directly to that register. If a register is associated with multiple triggers, then all associated triggers must be disabled to allow direct writes to the associated register. Setting bit Trigger[N] loads Trigger[N]'s associated registers Note: When Trigger[N] is enabled, writing to a register associated 2:0 Trigger[2:0] 0b000 B/G No R/W with Trigger[N] sends data to that register's shadow. Setting the Trigger[N] bit loads data from shadow. All triggers are processed immediately and simultaneously and then cleared. Trigger[0], [1], and [2] will always read as 0.
Reg29 (0x1D) ─ PRODUCT_ID Bit(s) Field Name Description Reset B/G Trig R/W
Lower eight bits of Product Number Note: These are read-only registers. However, as part of the special 7:0 PROD_ID[7:0] 0x4C No No R programming sequence for writing USID, a write command sequence is performed on one or both registers, but does not update them. See MIPI 6.6.2 for details.
Reg30 (0x1E) ─ MANUFACTURER_ID Bit(s) Field Name Description Reset B/G Trig R/W
Lower eight bits of MIPI Manufacturer ID Note: These are read-only registers. However, as part of the special 7:0 MFG_ID[7:0] 0xC6 No No R programming sequence for writing USID, a write command sequence is performed on one or both registers, but does not update them. See MIPI 6.6.2 for details. QPC1252Q Preliminary DS RevA | Subject to change without notice 9 of 17
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