Datasheet SAMA5D3 (Microchip) - 6

SAMA5D3 SERIES Table 2-1: Signal Description List (Continued) Signal Name Function Type Active Level External Bus Interface - EBI
D0–D15 Data Bus I/O — A0–A25 Address Bus Output — NWAIT External Wait Signal Input Low
Static Memory Controller - SMC
NCS0–NCS3 Chip Select Lines Output Low NWR0–NWR1 Write Signal Output Low NRD Read Signal Output Low NWE Write Enable Output Low NBS0–NBS1 Byte Mask Signal Output Low NANDOE NAND Flash Output Enable Output Low NANDWE NAND Flash Write Enable Output Low
DDR2/LPDDR Controller
DDR_VREF Reference Voltage Input — DDR_CALP Positive Calibration Reference Input — DDR_CALN Negative Calibration Reference Input — DDR_CK, DDR_CKN DDR2 differential clock Output — DDR_CKE DDR2 Clock Enable Output High DDR_CS DDR2 Controller Chip Select Output Low DDR_BA[2..0] Bank Select Output Low DDR_WE DDR2 Write Enable Output Low DDR_RAS, DDR_CAS Row and Column Signal Output Low DDR_A[13..0] DDR2 Address Bus Output — DDR_D[31..0] DDR2 Data Bus I/O — DQS[3..0] Differential Data Strobe I/O — DQSN[3..0] DQSN must be connected to DDR_VREF for DDR2 memories I/O — DQM[3..0] Write Data Mask Output —
High Speed Multimedia Card Interface - HSMCIx [2..0]
MCI0_CK, MCI1_CK, MCI2_CK Multimedia Card Clock I/O — MCI0_CDA, MCI1_CDA, MCI2_CDA Multimedia Card Command I/O — MCI0_DA[7..0] Multimedia Card 0 Data I/O — MCI1_DA[3..0] Multimedia Card 1 Data I/O — MCI2_DA[3..0) Multimedia Card 2 Data I/O — DS60001609B-page 6  2020 Microchip Technology Inc. Document Outline Description Features SAMA5D3 Device Differences 1. Block Diagram 2. Signal Description 3. Package and Pinout 3.1 324-ball LFBGA Package (15 x 15 x 1.4 mm, pitch 0.8 mm) 3.2 324-ball LFBGA Package Pinout 3.3 324-ball TFBGA Package (12 x 12 x 1.2 mm, pitch 0.5 mm) 3.4 324-ball TFBGA Package Pinout 3.5 Input/Output Description 4. Power Considerations 4.1 Power Supplies 4.2 Power Sequence Requirements 4.2.1 Power-up Considerations 4.2.2 Power-down Considerations 5. Memories 5.1 Embedded Memories 5.1.1 Internal SRAM 5.1.2 Internal ROM 5.1.3 Boot Strategies 5.2 External Memory 5.2.1 DDR2/LPDDR/LPDDR2 Interface 5.2.2 Static Memories and NAND Flash 6. Real-time Event Management 6.1 Embedded Characteristics 6.2 Real-time Event Mapping List 7. System Controller 7.1 Chip Identification 7.2 Backup Section 8. Peripherals 8.1 Peripheral Mapping 8.2 Peripheral Identifiers 8.3 Peripheral Signal Multiplexing on I/O Lines 8.4 Peripheral Clock Type 9. ARM Cortex-A5 9.1 Description 9.1.1 Power Management 9.1.1.1 Run Mode 9.1.1.2 Standby Mode 9.2 Embedded Characteristics 9.3 Block Diagram 9.4 Programmer Model 9.4.1 Processor Operating Modes 9.4.2 Processor Operating States 9.4.2.1 Switching State 9.4.3 Cortex-A5 Registers 9.4.3.1 CP15 Coprocessor 9.4.4 CP 15 Register Access 9.4.5 Addresses in the Cortex-A5 processor 9.5 Memory Management Unit 9.5.1 About the MMU 9.5.2 Memory Management System 9.5.2.1 Memory Types 9.5.3 TLB Organization 9.5.3.1 Micro TLB 9.5.3.2 Main TLB 9.5.4 Memory Access Sequence 9.5.5 Interaction with Memory System 9.5.6 External Aborts 9.5.6.1 External Aborts on Data Write 9.5.6.2 Synchronous and Asynchronous Aborts 9.5.7 MMU Software Accessible Registers 10. Debug and Test 10.1 Description 10.2 Embedded Characteristics 10.3 Block Diagram 10.4 Application Examples 10.4.1 Debug Environment 10.4.2 Test Environment 10.5 Debug and Test Pin Description 10.6 Functional Description 10.6.1 Test Pin 10.6.2 EmbeddedICE 10.6.3 JTAG Signal Description 10.6.4 Chip Access Using JTAG Connection 10.6.5 Debug Unit 10.6.6 IEEE 1149.1 JTAG Boundary Scan 10.7 Boundary JTAG ID Register 10.8 Cortex-A5 Debug Port Identification Code Register IDCODE 10.8.1 JTAG Debug Port (JTAG-DP) 10.8.2 JTAG-DP Device ID Code Register 10.8.3 Serial Wire Debug Port (SW-DP) 11. Standard Boot Strategies 11.1 Description 11.2 Flow Diagram 11.3 Chip Setup 11.4 NVM Boot 11.4.1 NVM Boot Sequence 11.4.2 NVM Bootloader Program Description 11.4.3 Valid Code Detection 11.4.3.1 ARM Exception Vectors Check 11.4.3.2 boot.bin File Check 11.4.4 Detailed Memory Boot Procedures 11.4.4.1 NAND Flash Boot: NAND Flash Detection 11.4.4.2 NAND Flash Boot: PMECC Error Detection and Correction 11.4.4.3 SD Card/eMMC Boot 11.4.4.4 SPI Flash Boot 11.4.4.5 TWI EEPROM Boot 11.4.5 Hardware and Software Constraints 11.5 SAM-BA Monitor 11.5.1 Command List 11.5.2 DBGU Serial Port 11.5.2.1 Supported External Crystal/External Clocks 11.5.2.2 Xmodem Protocol 11.5.3 USB Device Port 11.5.3.1 Supported External Crystal / External Clocks 11.5.3.2 USB Class 11.5.3.3 Enumeration Process 11.5.3.4 Communication Endpoints 12. Boot Sequence Controller (BSC) 12.1 Description 12.2 Embedded Characteristics 12.3 Product Dependencies 12.4 Boot Sequence Controller (BSC) Registers User Interface 12.4.1 Boot Sequence Controller Configuration Register 13. AXI Matrix (AXIMX) 13.1 Description 13.2 Embedded Characteristics 13.3 Operation 13.3.1 Remap 13.4 AXI Matrix (AXIMX) User Interface 13.4.1 AXI Matrix Remap Register 14. Bus Matrix (MATRIX) 14.1 Description 14.1.1 Matrix Masters 14.1.2 Matrix Slaves 14.1.3 Master to Slave Access 14.2 Embedded Characteristics 14.3 Memory Mapping 14.4 Special Bus Granting Techniques 14.5 No Default Master 14.6 Last Access Master 14.7 Fixed Default Master 14.8 Arbitration 14.8.1 Arbitration Scheduling 14.8.1.1 Undefined Length Burst Arbitration 14.8.1.2 Slot Cycle Limit Arbitration 14.8.2 Arbitration Priority Scheme 14.8.2.1 Fixed Priority Arbitration 14.8.2.2 Round-Robin Arbitration 14.9 Register Write Protection 14.10 Matrix (MATRIX) User Interface 14.10.1 MATRIX Master Configuration Registers 14.10.2 MATRIX Slave Configuration Registers 14.10.3 MATRIX Priority Registers A For Slaves 14.10.4 MATRIX Priority Registers B For Slaves 14.10.5 MATRIX Master Remap Control Register 14.10.6 MATRIX Write Protection Mode Register 14.10.7 MATRIX Write Protection Status Register 15. Special Function Registers (SFR) 15.1 Description 15.2 Embedded Characteristics 15.3 Special Function Registers (SFR) User Interface 15.3.1 DDR Configuration Register 15.3.2 OHCI Interrupt Configuration Register 15.3.3 OHCI Interrupt Status Register 15.3.4 Security Configuration Register 15.3.5 UTMI Clock Trimming Register 15.3.6 EBI Configuration Register 16. Advanced Interrupt Controller (AIC) 16.1 Description 16.2 Embedded Characteristics 16.3 Block Diagram 16.4 Application Block Diagram 16.5 AIC Detailed Block Diagram 16.6 I/O Line Description 16.7 Product Dependencies 16.7.1 I/O Lines 16.7.2 Power Management 16.7.3 Interrupt Sources 16.8 Functional Description 16.8.1 Interrupt Source Control 16.8.1.1 Interrupt Source Mode 16.8.1.2 Interrupt Source Enabling 16.8.1.3 Interrupt Clearing and Setting 16.8.1.4 Interrupt Status 16.8.1.5 Internal Interrupt Source Input Stage 16.8.1.6 External Interrupt Source Input Stage 16.8.2 Interrupt Latencies 16.8.2.1 External Interrupt Edge Triggered Source 16.8.2.2 External Interrupt Level Sensitive Source 16.8.2.3 Internal Interrupt Edge Triggered Source 16.8.2.4 Internal Interrupt Level Sensitive Source 16.8.3 Normal Interrupt 16.8.3.1 Priority Controller 16.8.3.2 Interrupt Nesting 16.8.3.3 Interrupt Handlers 16.8.4 Fast Interrupt 16.8.4.1 Fast Interrupt Source 16.8.4.2 Fast Interrupt Control 16.8.4.3 Fast Interrupt Handlers 16.8.4.4 Fast Forcing 16.8.5 Protect Mode 16.8.6 Spurious Interrupt 16.8.7 General Interrupt Mask 16.8.8 Register Write Protection 16.9 Advanced Interrupt Controller (AIC) User Interface 16.9.1 AIC Source Select Register 16.9.2 AIC Source Mode Register 16.9.3 AIC Source Vector Register 16.9.4 AIC Interrupt Vector Register 16.9.5 AIC FIQ Vector Register 16.9.6 AIC Interrupt Status Register 16.9.7 AIC Interrupt Pending Register 0 16.9.8 AIC Interrupt Pending Register 1 16.9.9 AIC Interrupt Pending Register 2 16.9.10 AIC Interrupt Pending Register 3 16.9.11 AIC Interrupt Mask Register 16.9.12 AIC Core Interrupt Status Register 16.9.13 AIC End of Interrupt Command Register 16.9.14 AIC Spurious Interrupt Vector Register 16.9.15 AIC Interrupt Enable Command Register 16.9.16 AIC Interrupt Disable Command Register 16.9.17 AIC Interrupt Clear Command Register 16.9.18 AIC Interrupt Set Command Register 16.9.19 AIC Fast Forcing Enable Register 16.9.20 AIC Fast Forcing Disable Register 16.9.21 AIC Fast Forcing Status Register 16.9.22 AIC Debug Control Register 16.9.23 AIC Write Protection Mode Register 16.9.24 AIC Write Protection Status Register 17. Watchdog Timer (WDT) 17.1 Description 17.2 Embedded Characteristics 17.3 Block Diagram 17.4 Functional Description 17.5 Watchdog Timer (WDT) User Interface 17.5.1 Watchdog Timer Control Register 17.5.2 Watchdog Timer Mode Register 17.5.3 Watchdog Timer Status Register 18. Reset Controller (RSTC) 18.1 Description 18.2 Embedded Characteristics 18.3 Block Diagram 18.4 Functional Description 18.4.1 Reset Controller Overview 18.4.2 NRST Manager 18.4.2.1 NRST Signal 18.4.2.2 NRST External Reset Control 18.4.3 BMS Sampling 18.4.4 Reset States 18.4.4.1 General Reset 18.4.4.2 Wake-up Reset 18.4.4.3 User Reset 18.4.4.4 Software Reset 18.4.4.5 Watchdog Reset 18.4.5 Reset State Priorities 18.5 Reset Controller (RSTC) User Interface 18.5.1 Reset Controller Control Register 18.5.2 Reset Controller Status Register 18.5.3 Reset Controller Mode Register 19. Shutdown Controller (SHDWC) 19.1 Description 19.2 Embedded Characteristics 19.3 Block Diagram 19.4 I/O Lines Description 19.5 Product Dependencies 19.5.1 Power Management 19.6 Functional Description 19.6.1 Wake-up Inputs 19.7 Shutdown Controller (SHDWC) User Interface 19.7.1 Shutdown Control Register 19.7.2 Shutdown Mode Register 19.7.3 Shutdown Status Register 20. General Purpose Backup Registers (GPBR) 20.1 Description 20.2 Embedded Characteristics 20.3 General Purpose Backup Registers (GPBR) User Interface 20.3.1 General Purpose Backup Register x 21. Periodic Interval Timer (PIT) 21.1 Description 21.2 Embedded Characteristics 21.3 Block Diagram 21.4 Functional Description 21.5 Periodic Interval Timer (PIT) User Interface 21.5.1 Periodic Interval Timer Mode Register 21.5.2 Periodic Interval Timer Status Register 21.5.3 Periodic Interval Timer Value Register 21.5.4 Periodic Interval Timer Image Register 22. Real-time Clock (RTC) 22.1 Description 22.2 Embedded Characteristics 22.3 Block Diagram 22.4 Product Dependencies 22.4.1 Power Management 22.4.2 Interrupt 22.5 Functional Description 22.5.1 Reference Clock 22.5.2 Timing 22.5.3 Alarm 22.5.4 Error Checking when Programming 22.5.5 Updating Time/Calendar 22.6 Real-time Clock (RTC) User Interface 22.6.1 RTC Control Register 22.6.2 RTC Mode Register 22.6.3 RTC Time Register 22.6.4 RTC Calendar Register 22.6.5 RTC Time Alarm Register 22.6.6 RTC Calendar Alarm Register 22.6.7 RTC Status Register 22.6.8 RTC Status Clear Command Register 22.6.9 RTC Interrupt Enable Register 22.6.10 RTC Interrupt Disable Register 22.6.11 RTC Interrupt Mask Register 22.6.12 RTC Valid Entry Register 23. Slow Clock Controller (SCKC) 23.1 Description 23.2 Embedded Characteristics 23.3 Block Diagram 23.4 Functional Description 23.4.1 Switching from Embedded 32 kHz RC Oscillator to 32.768 kHz Crystal Oscillator 23.4.2 Bypassing the 32.768 kHz Crystal Oscillator 23.4.3 Switching from 32.768 kHz Crystal Oscillator to Embedded 32 kHz RC Oscillator 23.5 Slow Clock Controller (SCKC) User Interface 23.5.1 Slow Clock Controller Configuration Register 24. Fuse Controller (FUSE) 24.1 Description 24.2 Embedded Characteristics 24.2.1 FUSE Bit Mapping 24.2.2 Special Functions 24.3 Block Diagram 24.4 Functional Description 24.4.1 Fuse Reading 24.4.2 Fuse Programming 24.4.3 Fuse Masking 24.5 Fuse Controller (FUSE) User Interface 24.5.1 Fuse Control Register 24.5.2 Fuse Mode Register 24.5.3 Fuse Index Register 24.5.4 Fuse Data Register 24.5.5 Fuse Status Register 25. Clock Generator 25.1 Description 25.2 Embedded Characteristics 25.3 Block Diagram 25.4 Slow Clock 25.4.1 Embedded 32 kHz (typical) RC Oscillator 25.4.2 32.768 kHz Crystal Oscillator 25.5 Main Clock 25.5.1 12 MHz RC Oscillator 25.5.2 12 MHz RC Oscillator Clock Frequency Adjustment 25.5.3 8 to 48 MHz Crystal Oscillator 25.5.4 Main Clock Source Selection 25.5.5 Bypassing the 8 to 48 MHz Crystal Oscillator 25.5.6 Main Clock Frequency Counter 25.5.7 Switching Main Clock Between the RC Oscillator and the Crystal Oscillator 25.6 Divider and PLLA Block 25.6.1 Divider and Phase Lock Loop Programming 25.7 UTMI Phase Lock Loop Programming 26. Power Management Controller (PMC) 26.1 Description 26.2 Embedded Characteristics 26.3 Block Diagram 26.4 Master Clock Controller 26.5 Processor Clock Controller 26.6 LCDC Clock Controller 26.7 USB Device and Host Clocks 26.8 DDR2/LPDDR/LPDDR2 Clock 26.9 Software Modem Clock 26.10 Fast Startup from Ultra Low-power (ULP) Mode 26.11 Peripheral Clock Controller 26.12 Programmable Clock Controller 26.13 Main Clock Failure Detector 26.14 Programming Sequence 26.15 Clock Switching Details 26.15.1 Master Clock Switching Timings 26.15.2 Clock Switching Waveforms 26.16 Register Write Protection 26.17 Power Management Controller (PMC) User Interface 26.17.1 PMC System Clock Enable Register 26.17.2 PMC System Clock Disable Register 26.17.3 PMC System Clock Status Register 26.17.4 PMC Peripheral Clock Enable Register 0 26.17.5 PMC Peripheral Clock Disable Register 0 26.17.6 PMC Peripheral Clock Status Register 0 26.17.7 PMC UTMI Clock Configuration Register 26.17.8 PMC Clock Generator Main Oscillator Register 26.17.9 PMC Clock Generator Main Clock Frequency Register 26.17.10 PMC Clock Generator PLLA Register 26.17.11 PMC Master Clock Register 26.17.12 PMC USB Clock Register 26.17.13 PMC SMD Clock Register 26.17.14 PMC Programmable Clock Register 26.17.15 PMC Interrupt Enable Register 26.17.16 PMC Interrupt Disable Register 26.17.17 PMC Status Register 26.17.18 PMC Interrupt Mask Register 26.17.19 PMC Fault Output Clear Register 26.17.20 PLL Charge Pump Current Register 26.17.21 PMC Write Protection Mode Register 26.17.22 PMC Write Protection Status Register 26.17.23 PMC Peripheral Clock Enable Register 1 26.17.24 PMC Peripheral Clock Disable Register 1 26.17.25 PMC Peripheral Clock Status Register 1 26.17.26 PMC Peripheral Control Register 26.17.27 PMC Oscillator Calibration Register 27. Parallel Input/Output Controller (PIO) 27.1 Description 27.2 Embedded Characteristics 27.3 Block Diagram 27.4 Product Dependencies 27.4.1 Pin Multiplexing 27.4.2 External Interrupt Lines 27.4.3 Power Management 27.4.4 Interrupt Sources 27.5 Functional Description 27.5.1 Pull-up and Pull-down Resistor Control 27.5.2 I/O Line or Peripheral Function Selection 27.5.3 Peripheral A or B or C or D Selection 27.5.4 Output Control 27.5.5 Synchronous Data Output 27.5.6 Multi-Drive Control (Open Drain) 27.5.7 Output Line Timings 27.5.8 Inputs 27.5.9 Input Glitch and Debouncing Filters 27.5.10 Input Edge/Level Interrupt 27.5.11 I/O Lines Lock 27.5.12 Programmable I/O Drive 27.5.13 Programmable Schmitt Trigger 27.5.14 I/O Lines Programming Example 27.5.15 Register Write Protection 27.6 Parallel Input/Output Controller (PIO) User Interface 27.6.1 PIO Enable Register 27.6.2 PIO Disable Register 27.6.3 PIO Status Register 27.6.4 PIO Output Enable Register 27.6.5 PIO Output Disable Register 27.6.6 PIO Output Status Register 27.6.7 PIO Input Filter Enable Register 27.6.8 PIO Input Filter Disable Register 27.6.9 PIO Input Filter Status Register 27.6.10 PIO Set Output Data Register 27.6.11 PIO Clear Output Data Register 27.6.12 PIO Output Data Status Register 27.6.13 PIO Pin Data Status Register 27.6.14 PIO Interrupt Enable Register 27.6.15 PIO Interrupt Disable Register 27.6.16 PIO Interrupt Mask Register 27.6.17 PIO Interrupt Status Register 27.6.18 PIO Multi-driver Enable Register 27.6.19 PIO Multi-driver Disable Register 27.6.20 PIO Multi-driver Status Register 27.6.21 PIO Pull-Up Disable Register 27.6.22 PIO Pull-Up Enable Register 27.6.23 PIO Pull-Up Status Register 27.6.24 PIO Peripheral ABCD Select Register 1 27.6.25 PIO Peripheral ABCD Select Register 2 27.6.26 PIO Input Filter Slow Clock Disable Register 27.6.27 PIO Input Filter Slow Clock Enable Register 27.6.28 PIO Input Filter Slow Clock Status Register 27.6.29 PIO Slow Clock Divider Debouncing Register 27.6.30 PIO Pad Pull-Down Disable Register 27.6.31 PIO Pad Pull-Down Enable Register 27.6.32 PIO Pad Pull-Down Status Register 27.6.33 PIO Output Write Enable Register 27.6.34 PIO Output Write Disable Register 27.6.35 PIO Output Write Status Register 27.6.36 PIO Additional Interrupt Modes Enable Register 27.6.37 PIO Additional Interrupt Modes Disable Register 27.6.38 PIO Additional Interrupt Modes Mask Register 27.6.39 PIO Edge Select Register 27.6.40 PIO Level Select Register 27.6.41 PIO Edge/Level Status Register 27.6.42 PIO Falling Edge/Low-Level Select Register 27.6.43 PIO Rising Edge/High-Level Select Register 27.6.44 PIO Fall/Rise - Low/High Status Register 27.6.45 PIO Lock Status Register 27.6.46 PIO Write Protection Mode Register 27.6.47 PIO Write Protection Status Register 27.6.48 PIO Schmitt Trigger Register 27.6.49 PIO I/O Drive Register 1 27.6.50 PIO I/O Drive Register 2 28. External Memories 28.1 Multi-port DDR-SDRAM Controller (MPDDRC) 28.1.1 Description 28.1.2 MPDDR Controller Block Diagram 28.1.3 I/O Lines Description 28.1.4 Product Dependencies 28.1.5 Implementation Example 28.1.5.1 2x16-bit DDR2 28.1.5.2 2x16-bit LPDDR2 28.2 External Bus Interface (EBI) 28.2.1 Description 28.2.2 Implementation Examples 28.2.2.1 8-bit NAND Flash 28.2.2.2 16-bit NAND Flash 28.2.2.3 NOR Flash on NCS0 29. Multi-port DDR-SDRAM Controller (MPDDRC) 29.1 Description 29.2 Embedded Characteristics 29.3 MPDDRC Module Diagram 29.4 Product Dependencies, Initialization Sequence 29.4.1 Low-power DDR1-SDRAM Initialization 29.4.2 DDR2-SDRAM Initialization 29.4.3 Low-power DDR2-SDRAM Initialization 29.5 Functional Description 29.5.1 DDR-SDRAM Controller Write Cycle 29.5.2 DDR-SDRAM Controller Read Cycle 29.5.2.1 All Banks Auto Refresh 29.5.2.2 Per-bank Auto Refresh 29.5.2.3 Adjust Auto Refresh Rate 29.5.3 Power Management 29.5.3.1 Self-refresh Mode 29.5.3.2 Power-down Mode 29.5.3.3 Deep Power-down Mode 29.5.3.4 Reset Mode 29.5.4 Multi-port Functionality 29.5.5 Scrambling/Unscrambling Function 29.5.6 Register Write Protection 29.6 Software Interface/SDRAM Organization, Address Mapping 29.6.1 DDR-SDRAM Address Mapping for 32-bit Memory Data Bus Width 29.7 AHB Multi-port DDR-SDRAM Controller (MPDDRC) User Interface 29.7.1 MPDDRC Mode Register 29.7.2 MPDDRC Refresh Timer Register 29.7.3 MPDDRC Configuration Register 29.7.4 MPDDRC Timing Parameter 0 Register 29.7.5 MPDDRC Timing Parameter 1 Register 29.7.6 MPDDRC Timing Parameter 2 Register 29.7.7 MPDDRC Low-power Register 29.7.8 MPDDRC Memory Device Register 29.7.9 MPDDRC High Speed Register 29.7.10 MPDDRC Low-power DDR2 Low-power Register 29.7.11 MPDDRC Low-power DDR2 Calibration and MR4 Register 29.7.12 MPDDRC Low-power DDR2 Timing Calibration Register 29.7.13 MPDDRC I/O Calibration Register 29.7.14 MPDDRC OCMS Register 29.7.15 MPDDRC OCMS KEY1 Register 29.7.16 MPDDRC OCMS KEY2 Register 29.7.17 MPDDRC Write Protection Mode Register 29.7.18 MPDDRC Write Protection Status Register 29.7.19 MPDDRC DLL Master Offset Register 29.7.20 MPDDRC DLL Slave Offset Register 29.7.21 MPDDRC DLL Master Status Register 29.7.22 MPDDRC DLL Status Slave x Register 30. Static Memory Controller (SMC) 30.1 Description 30.2 Embedded Characteristics 30.3 Block Diagram 30.4 I/O Lines Description 30.5 Multiplexed Signals 30.6 Application Example 30.6.1 Hardware Interface 30.7 Product Dependencies 30.7.1 I/O Lines 30.7.2 Power Management 30.7.3 Interrupt Sources 30.8 External Memory Mapping 30.9 Connection to External Devices 30.9.1 Data Bus Width 30.9.2 Byte Write or Byte Select Access 30.9.2.1 Byte Write Access 30.9.2.2 Byte Select Access 30.9.2.3 Signal Multiplexing 30.10 Standard Read and Write Protocols 30.10.1 Read Waveforms 30.10.1.1 NRD Waveform 30.10.1.2 NCS Waveform 30.10.1.3 Read Cycle 30.10.2 Read Mode 30.10.2.1 Read is Controlled by NRD (READ_MODE = 1) 30.10.2.2 Read is Controlled by NCS (READ_MODE = 0) 30.10.3 Write Waveforms 30.10.3.1 NWE Waveforms 30.10.3.2 NCS Waveforms 30.10.3.3 Write Cycle 30.10.4 Write Mode 30.10.4.1 Write is Controlled by NWE (WRITE_MODE = 1) 30.10.4.2 Write is Controlled by NCS (WRITE_MODE = 0) 30.10.5 Coding Timing Parameters 30.10.6 Reset Values of Timing Parameters 30.10.7 Usage Restriction 30.10.7.1 For Read Operations 30.10.7.2 For Write Operations 30.10.7.3 For Read and Write Operations 30.11 Scrambling/Unscrambling Function 30.12 Automatic Wait States 30.12.1 Chip Select Wait States 30.12.2 Early Read Wait State 30.12.3 Reload User Configuration Wait State 30.12.3.1 User Procedure 30.12.3.2 Slow Clock Mode Transition 30.12.4 Read to Write Wait State 30.13 Data Float Wait States 30.13.1 READ_MODE 30.13.2 TDF Optimization Enabled (TDF_MODE = 1) 30.13.3 TDF Optimization Disabled (TDF_MODE = 0) 30.14 External Wait 30.14.1 Restriction 30.14.2 Frozen Mode 30.14.3 Ready Mode 30.14.4 NWAIT Latency and Read/Write Timings 30.15 Slow Clock Mode 30.15.1 Slow Clock Mode Waveforms 30.15.2 Switching from (to) Slow Clock Mode to (from) Normal Mode 30.16 Register Write Protection 30.17 NFC Operations 30.17.1 NFC Overview 30.17.2 NFC Control Registers 30.17.2.1 Building NFC Address Command Example 30.17.2.2 NFC Address Command 30.17.2.3 NFC Data Address 30.17.2.4 NFC DATA Status 30.17.3 NFC Initialization 30.17.3.1 NFC Timing Engine 30.17.4 NFC SRAM 30.17.4.1 NFC SRAM Mapping 30.17.4.2 NFC SRAM Access Prioritization Algorithm 30.17.5 NAND Flash Operations 30.17.5.1 Page Read 30.17.5.2 Program Page 30.18 PMECC Controller Functional Description 30.18.1 MLC/SLC Write Page Operation Using PMECC 30.18.1.1 SLC/MLC Write Operation with Spare Enable Bit Set 30.18.1.2 SLC/MLC Write Operation with Spare Disable 30.18.2 MLC/SLC Read Page Operation Using PMECC 30.18.2.1 MLC/SLC Read Operation with Spare Decoding 30.18.2.2 MLC/SLC Read Operation 30.18.2.3 MLC/SLC User Read ECC Area 30.18.2.4 MLC Controller Working with NFC 30.19 Software Implementation 30.19.1 Remainder Substitution Procedure 30.19.2 Finding the Error Location Polynomial Sigma(x) 30.19.3 Finding the Error Position 30.19.3.1 Error Location 30.20 Static Memory Controller (SMC) User Interface 30.20.1 NFC Configuration Register 30.20.2 NFC Control Register 30.20.3 NFC Status Register 30.20.4 NFC Interrupt Enable Register 30.20.5 NFC Interrupt Disable Register 30.20.6 NFC Interrupt Mask Register 30.20.7 NFC Address Cycle Zero Register 30.20.8 NFC Bank Register 30.20.9 PMECC Configuration Register 30.20.10 PMECC Spare Area Size Register 30.20.11 PMECC Start Address Register 30.20.12 PMECC End Address Register 30.20.13 PMECC Control Register 30.20.14 PMECC Status Register 30.20.15 PMECC Interrupt Enable Register 30.20.16 PMECC Interrupt Disable Register 30.20.17 PMECC Interrupt Mask Register 30.20.18 PMECC Interrupt Status Register 30.20.19 PMECC Redundancy x Register 30.20.20 PMECC Remainder x Register 30.20.21 PMECC Error Location Configuration Register 30.20.22 PMECC Error Location Primitive Register 30.20.23 PMECC Error Location Enable Register 30.20.24 PMECC Error Location Disable Register 30.20.25 PMECC Error Location Status Register 30.20.26 PMECC Error Location Interrupt Enable Register 30.20.27 PMECC Error Location Interrupt Disable Register 30.20.28 PMECC Error Location Interrupt Mask Register 30.20.29 PMECC Error Location Interrupt Status Register 30.20.30 PMECC Error Location SIGMA0 Register 30.20.31 PMECC Error Location SIGMAx Register 30.20.32 PMECC Error Location x Register 30.20.33 Setup Register 30.20.34 Pulse Register 30.20.35 Cycle Register 30.20.36 Timings Register 30.20.37 Mode Register 30.20.38 Off Chip Memory Scrambling Register 30.20.39 Off Chip Memory Scrambling Key1 Register 30.20.40 Off Chip Memory Scrambling Key2 Register 30.20.41 Write Protection Mode Register 30.20.42 Write Protection Status Register 31. DMA Controller (DMAC) 31.1 Description 31.2 Embedded Characteristics 31.3 DMA Controller Peripheral Connections 31.3.1 DMA Controller 0 31.3.2 DMA Controller 1 31.4 Block Diagram 31.5 Product Dependencies 31.5.1 Interrupt Sources 31.6 Functional Description 31.6.1 Basic Definitions 31.6.2 Memory Peripherals 31.6.3 Handshaking Interface 31.6.3.1 Software Handshaking 31.6.4 DMAC Transfer Types 31.6.4.1 Multi-buffer Transfers 31.6.4.2 Programming DMAC for Multiple Buffer Transfers 31.6.4.3 Ending Multi-buffer Transfers 31.6.5 Programming a Channel 31.6.5.1 Programming Examples 31.6.6 Disabling a Channel Prior to Transfer Completion 31.6.6.1 Abnormal Transfer Termination 31.6.7 Register Write Protection 31.7 DMAC Software Requirements 31.8 DMA Controller (DMAC) User Interface 31.8.1 DMAC Global Configuration Register 31.8.2 DMAC Enable Register 31.8.3 DMAC Software Single Request Register 31.8.4 DMAC Software Chunk Transfer Request Register 31.8.5 DMAC Software Last Transfer Flag Register 31.8.6 DMAC Error, Buffer Transfer and Chained Buffer Transfer Interrupt Enable Register 31.8.7 DMAC Error, Buffer Transfer and Chained Buffer Transfer Interrupt Disable Register 31.8.8 DMAC Error, Buffer Transfer and Chained Buffer Transfer Interrupt Mask Register 31.8.9 DMAC Error, Buffer Transfer and Chained Buffer Transfer Status Register 31.8.10 DMAC Channel Handler Enable Register 31.8.11 DMAC Channel Handler Disable Register 31.8.12 DMAC Channel Handler Status Register 31.8.13 DMAC Channel x [x = 0..7] Source Address Register 31.8.14 DMAC Channel x [x = 0..7] Destination Address Register 31.8.15 DMAC Channel x [x = 0..7] Descriptor Address Register 31.8.16 DMAC Channel x [x = 0..7] Control A Register 31.8.17 DMAC Channel x [x = 0..7] Control B Register 31.8.18 DMAC Channel x [x = 0..7] Configuration Register 31.8.19 DMAC Channel x [x = 0..7] Source Picture-in-Picture Configuration Register 31.8.20 DMAC Channel x [x = 0..7] Destination Picture-in-Picture Configuration Register 31.8.21 DMAC Write Protection Mode Register 31.8.22 DMAC Write Protection Status Register 32. LCD Controller (LCDC) 32.1 Description 32.2 Embedded Characteristics 32.3 Block Diagram 32.4 I/O Lines Description 32.5 Product Dependencies 32.5.1 I/O Lines 32.5.2 Power Management 32.5.3 Interrupt Sources 32.6 Functional Description 32.6.1 Timing Engine Configuration 32.6.1.1 Pixel Clock Period Configuration 32.6.1.2 Horizontal and Vertical Synchronization Configuration 32.6.1.3 Timing Engine Power Up Software Operation 32.6.1.4 Timing Engine Power Down Software Operation 32.6.2 DMA Software Operations 32.6.2.1 DMA Channel Descriptor (DSCR) Alignment and Structure 32.6.2.2 Programming a DMA Channel 32.6.2.3 Disabling a DMA channel 32.6.2.4 DMA Dynamic Linking of a New Transfer Descriptor 32.6.2.5 DMA Interrupt Generation 32.6.2.6 DMA Address Alignment Requirements 32.6.3 Overlay Software Configuration 32.6.3.1 System Bus Access Attributes 32.6.3.2 Color Attributes 32.6.3.3 Window Position, Size, Scaling and Striding Attributes 32.6.3.4 Overlay Blender Attributes 32.6.3.5 Overlay Attributes Software Operation 32.6.4 RGB Frame Buffer Memory Bitmap 32.6.4.1 1 bpp Through Color Lookup Table 32.6.4.2 2 bpp Through Color Lookup Table 32.6.4.3 4 bpp Through Color Lookup Table 32.6.4.4 8 bpp Through Color Lookup Table 32.6.4.5 12 bpp Memory Mapping, RGB 4:4:4 32.6.4.6 16 bpp Memory Mapping with Alpha Channel, ARGB 4:4:4:4 32.6.4.7 16 bpp Memory Mapping with Alpha Channel, RGBA 4:4:4:4 32.6.4.8 16 bpp Memory Mapping with Alpha Channel, RGB 5:6:5 32.6.4.9 16 bpp Memory Mapping with Transparency Bit, ARGB 1:5:5:5 32.6.4.10 18 bpp Unpacked Memory Mapping with Transparency Bit, RGB 6:6:6 32.6.4.11 18 bpp Packed Memory Mapping with Transparency Bit, RGB 6:6:6 32.6.4.12 19 bpp Unpacked Memory Mapping with Transparency Bit, RGB 1:6:6:6 32.6.4.13 19 bpp Packed Memory Mapping with Transparency Bit, ARGB 1:6:6:6 32.6.4.14 24 bpp Unpacked Memory Mapping, RGB 8:8:8 32.6.4.15 24 bpp Packed Memory Mapping, RGB 8:8:8 32.6.4.16 25 bpp Memory Mapping, ARGB 1:8:8:8 32.6.4.17 32 bpp Memory Mapping, ARGB 8:8:8:8 32.6.4.18 32 bpp Memory Mapping, RGBA 8:8:8:8 32.6.5 YUV Frame Buffer Memory Mapping 32.6.5.1 AYCbCr 4:4:4 Interleaved Frame Buffer Memory Mapping 32.6.5.2 4:2:2 Interleaved Mode Frame Buffer Memory Mapping 32.6.5.3 4:2:2 Semiplanar Mode Frame Buffer Memory Mapping 32.6.5.4 4:2:2 Planar Mode Frame Buffer Memory Mapping 32.6.5.5 4:2:0 Planar Mode Frame Buffer Memory Mapping 32.6.5.6 4:2:0 Semiplanar Frame Buffer Memory Mapping 32.6.6 Chrominance Upsampling Unit 32.6.6.1 Chrominance Upsampling Algorithm 32.6.7 Line and Pixel Striding 32.6.7.1 Line Striding 32.6.7.2 Pixel Striding 32.6.8 Color Space Conversion Unit 32.6.9 Two Dimension Scaler 32.6.9.1 Video Scaler Description 32.6.9.2 Horizontal Scaler 32.6.9.3 Vertical Scaler 32.6.10 Hardware Cursor 32.6.11 Color Combine Unit 32.6.11.1 Window Overlay 32.6.11.2 Base Layer with Window Overlay Optimization 32.6.11.3 Overlay Blending 32.6.11.4 Global Alpha Blender 32.6.11.5 Window Blending 32.6.11.6 Color Keying 32.6.12 LCDC PWM Controller 32.6.13 Post Processing Controller 32.6.14 LCD Overall Performance 32.6.14.1 Color Lookup Table (CLUT) 32.6.14.2 RGB Mode Fetch Performance 32.6.14.3 YUV Mode Fetch Performance 32.6.15 Input FIFO 32.6.16 Output FIFO 32.6.17 Output Timing Generation 32.6.17.1 Active Display Timing Mode 32.6.18 Output Format 32.6.18.1 Active Mode Output Pin Assignment 32.7 LCD Controller (LCDC) User Interface 32.7.1 LCD Controller Configuration Register 0 32.7.2 LCD Controller Configuration Register 1 32.7.3 LCD Controller Configuration Register 2 32.7.4 LCD Controller Configuration Register 3 32.7.5 LCD Controller Configuration Register 4 32.7.6 LCD Controller Configuration Register 5 32.7.7 LCD Controller Configuration Register 6 32.7.8 LCD Controller Enable Register 32.7.9 LCD Controller Disable Register 32.7.10 LCD Controller Status Register 32.7.11 LCD Controller Interrupt Enable Register 32.7.12 LCD Controller Interrupt Disable Register 32.7.13 LCD Controller Interrupt Mask Register 32.7.14 LCD Controller Interrupt Status Register 32.7.15 LCD Controller Attribute Register 32.7.16 Base Layer Channel Enable Register 32.7.17 Base Layer Channel Disable Register 32.7.18 Base Layer Channel Status Register 32.7.19 Base Layer Interrupt Enable Register 32.7.20 Base Layer Interrupt Disable Register 32.7.21 Base Layer Interrupt Mask Register 32.7.22 Base Layer Interrupt Status Register 32.7.23 Base DMA Head Register 32.7.24 Base DMA Address Register 32.7.25 Base DMA Control Register 32.7.26 Base DMA Next Register 32.7.27 Base Layer Configuration Register 0 32.7.28 Base Layer Configuration Register 1 32.7.29 Base Layer Configuration Register 2 32.7.30 Base Layer Configuration Register 3 32.7.31 Base Layer Configuration Register 4 32.7.32 Base Layer Configuration Register 5 32.7.33 Base Layer Configuration Register 6 32.7.34 Overlay 1 Channel Enable Register 32.7.35 Overlay 1 Channel Disable Register 32.7.36 Overlay 1 Channel Status Register 32.7.37 Overlay 1 Interrupt Enable Register 32.7.38 Overlay 1 Interrupt Disable Register 32.7.39 Overlay 1 Interrupt Mask Register 32.7.40 Overlay 1 Interrupt Status Register 32.7.41 Overlay 1 Head Register 32.7.42 Overlay 1 Address Register 32.7.43 Overlay 1 Control Register 32.7.44 Overlay 1 Next Register 32.7.45 Overlay 1 Configuration Register 0 32.7.46 Overlay 1 Configuration Register 1 32.7.47 Overlay 1 Configuration Register 2 32.7.48 Overlay 1 Configuration Register 3 32.7.49 Overlay 1 Configuration Register 4 32.7.50 Overlay 1 Configuration Register 5 32.7.51 Overlay 1 Configuration Register 6 32.7.52 Overlay 1 Configuration Register 7 32.7.53 Overlay 1 Configuration Register 8 32.7.54 Overlay 1 Configuration Register 9 32.7.55 Overlay 2 Channel Enable Register 32.7.56 Overlay 2 Channel Disable Register 32.7.57 Overlay 2 Channel Status Register 32.7.58 Overlay 2 Interrupt Enable Register 32.7.59 Overlay 2 Interrupt Disable Register 32.7.60 Overlay 2 Interrupt Mask Register 32.7.61 Overlay 2 Interrupt Status Register 32.7.62 Overlay 2 Head Register 32.7.63 Overlay 2 Address Register 32.7.64 Overlay 2 Control Register 32.7.65 Overlay 2 Next Register 32.7.66 Overlay 2 Configuration Register 0 32.7.67 Overlay 2 Configuration Register 1 32.7.68 Overlay 2 Configuration Register 2 32.7.69 Overlay 2 Configuration Register 3 32.7.70 Overlay 2 Configuration Register 4 32.7.71 Overlay 2 Configuration Register 5 32.7.72 Overlay 2 Configuration Register 6 32.7.73 Overlay 2 Configuration Register 7 32.7.74 Overlay 2 Configuration Register 8 32.7.75 Overlay 2 Configuration Register 9 32.7.76 High End Overlay Channel Enable Register 32.7.77 High End Overlay Channel Disable Register 32.7.78 High End Overlay Channel Status Register 32.7.79 High End Overlay Interrupt Enable Register 32.7.80 High End Overlay Interrupt Disable Register 32.7.81 High End Overlay Interrupt Mask Register 32.7.82 High End Overlay Interrupt Status Register 32.7.83 High End Overlay DMA Head Register 32.7.84 High End Overlay DMA Address Register 32.7.85 High End Overlay DMA Control Register 32.7.86 High End Overlay DMA Next Register 32.7.87 High End Overlay U-UV DMA Head Register 32.7.88 High End Overlay U-UV DMA Address Register 32.7.89 High End Overlay U-UV DMA Control Register 32.7.90 High End Overlay U-UV DMA Next Register 32.7.91 High End Overlay V DMA Head Register 32.7.92 High End Overlay V DMA Address Register 32.7.93 High End Overlay V DMA Control Register 32.7.94 High End Overlay V DMA Next Register 32.7.95 High End Overlay Configuration Register 0 32.7.96 High End Overlay Configuration Register 1 32.7.97 High End Overlay Configuration Register 2 32.7.98 High End Overlay Configuration Register 3 32.7.99 High End Overlay Configuration Register 4 32.7.100 High End Overlay Configuration Register 5 32.7.101 High End Overlay Configuration Register 6 32.7.102 High End Overlay Configuration Register 7 32.7.103 High End Overlay Configuration Register 8 32.7.104 High End Overlay Configuration Register 9 32.7.105 High End Overlay Configuration Register 10 32.7.106 High End Overlay Configuration Register 11 32.7.107 High End Overlay Configuration Register 12 32.7.108 High End Overlay Configuration Register 13 32.7.109 High End Overlay Configuration Register 14 32.7.110 High End Overlay Configuration Register 15 32.7.111 High End Overlay Configuration Register 16 32.7.112 High End Overlay Configuration Register 17 32.7.113 High End Overlay Configuration Register 18 32.7.114 High End Overlay Configuration Register 19 32.7.115 High End Overlay Configuration Register 20 32.7.116 High End Overlay Configuration Register 21 32.7.117 High End Overlay Configuration Register 22 32.7.118 High End Overlay Configuration Register 23 32.7.119 High End Overlay Configuration Register 24 32.7.120 High End Overlay Configuration Register 25 32.7.121 High End Overlay Configuration Register 26 32.7.122 High End Overlay Configuration Register 27 32.7.123 High End Overlay Configuration Register 28 32.7.124 High End Overlay Configuration Register 29 32.7.125 High End Overlay Configuration Register 30 32.7.126 High End Overlay Configuration Register 31 32.7.127 High End Overlay Configuration Register 32 32.7.128 High End Overlay Configuration Register 33 32.7.129 High End Overlay Configuration Register 34 32.7.130 High End Overlay Configuration Register 35 32.7.131 High End Overlay Configuration Register 36 32.7.132 High End Overlay Configuration Register 37 32.7.133 High End Overlay Configuration Register 38 32.7.134 High End Overlay Configuration Register 39 32.7.135 High End Overlay Configuration Register 40 32.7.136 High End Overlay Configuration Register 41 32.7.137 Hardware Cursor Channel Enable Register 32.7.138 Hardware Cursor Channel Disable Register 32.7.139 Hardware Cursor Channel Status Register 32.7.140 Hardware Cursor Interrupt Enable Register 32.7.141 Hardware Cursor Interrupt Disable Register 32.7.142 Hardware Cursor Interrupt Mask Register 32.7.143 Hardware Cursor Interrupt Status Register 32.7.144 Hardware Cursor Head Register 32.7.145 Hardware Cursor Address Register 32.7.146 Hardware Cursor Control Register 32.7.147 Hardware Cursor Next Register 32.7.148 Hardware Cursor Configuration Register 0 32.7.149 Hardware Cursor Configuration Register 1 32.7.150 Hardware Cursor Configuration Register 2 32.7.151 Hardware Cursor Configuration Register 3 32.7.152 Hardware Cursor Configuration Register 4 32.7.153 Hardware Cursor Configuration Register 6 32.7.154 Hardware Cursor Configuration Register 7 32.7.155 Hardware Cursor Configuration Register 8 32.7.156 Hardware Cursor Configuration Register 9 32.7.157 Post Processing Channel Enable Register 32.7.158 Post Processing Channel Disable Register 32.7.159 Post Processing Channel Status Register 32.7.160 Post Processing Interrupt Enable Register 32.7.161 Post Processing Interrupt Disable Register 32.7.162 Post Processing Interrupt Mask Register 32.7.163 Post Processing Interrupt Status Register 32.7.164 Post Processing Head Register 32.7.165 Post Processing Address Register 32.7.166 Post Processing Control Register 32.7.167 Post Processing Next Register 32.7.168 Post Processing Configuration Register 0 32.7.169 Post Processing Configuration Register 1 32.7.170 Post Processing Configuration Register 2 32.7.171 Post Processing Configuration Register 3 32.7.172 Post Processing Configuration Register 4 32.7.173 Post Processing Configuration Register 5 32.7.174 Base CLUT Register x 32.7.175 Overlay 1 CLUT Register x 32.7.176 Overlay 2 CLUT Register x 32.7.177 High End Overlay CLUT Register x 32.7.178 Hardware Cursor CLUT Register x 33. Image Sensor Interface (ISI) 33.1 Description 33.2 Embedded Characteristics 33.3 Block Diagram 33.4 Product Dependencies 33.4.1 I/O Lines 33.4.2 Power Management 33.4.3 Interrupt Sources 33.5 Functional Description 33.5.1 Data Timing 33.5.1.1 VSYNC/HSYNC Data Timing 33.5.1.2 SAV/EAV Data Timing 33.5.2 Data Ordering 33.5.3 Clocks 33.5.4 Preview Path 33.5.4.1 Scaling, Decimation (Subsampling) 33.5.4.2 Color Space Conversion 33.5.4.3 Memory Interface 33.5.4.4 FIFO and DMA Features 33.5.5 Codec Path 33.5.5.1 Color Space Conversion 33.5.5.2 Memory Interface 33.5.5.3 DMA Features 33.6 Register Write Protection 33.7 Image Sensor Interface (ISI) User Interface 33.7.1 ISI Configuration 1 Register 33.7.2 ISI Configuration 2 Register 33.7.3 ISI Preview Size Register 33.7.4 ISI Preview Decimation Factor Register 33.7.5 ISI Color Space Conversion YCrCb to RGB Set 0 Register 33.7.6 ISI Color Space Conversion YCrCb to RGB Set 1 Register 33.7.7 ISI Color Space Conversion RGB to YCrCb Set 0 Register 33.7.8 ISI Color Space Conversion RGB to YCrCb Set 1 Register 33.7.9 ISI Color Space Conversion RGB to YCrCb Set 2 Register 33.7.10 ISI Control Register 33.7.11 ISI Status Register 33.7.12 ISI Interrupt Enable Register 33.7.13 ISI Interrupt Disable Register 33.7.14 ISI Interrupt Mask Register 33.7.15 DMA Channel Enable Register 33.7.16 DMA Channel Disable Register 33.7.17 DMA Channel Status Register 33.7.18 DMA Preview Base Address Register 33.7.19 DMA Preview Control Register 33.7.20 DMA Preview Descriptor Address Register 33.7.21 DMA Codec Base Address Register 33.7.22 DMA Codec Control Register 33.7.23 DMA Codec Descriptor Address Register 33.7.24 ISI Write Protection Mode Register 33.7.25 ISI Write Protection Status Register 34. USB High Speed Device Port (UDPHS) 34.1 Description 34.2 Embedded Characteristics 34.3 Block Diagram 34.4 Typical Connection 34.5 Product Dependencies 34.5.1 Power Management 34.5.2 Interrupt Sources 34.6 Functional Description 34.6.1 UTMI transceivers Sharing 34.6.2 USB V2.0 High Speed Device Port Introduction 34.6.3 USB V2.0 High Speed Transfer Types 34.6.4 USB Transfer Event Definitions 34.6.5 USB V2.0 High Speed BUS Transactions 34.6.6 Endpoint Configuration 34.6.7 DPRAM Management 34.6.8 Transfer With DMA 34.6.9 Transfer Without DMA 34.6.10 Handling Transactions with USB V2.0 Device Peripheral 34.6.10.1 Setup Transaction 34.6.10.2 NYET 34.6.10.3 Data IN 34.6.10.4 Data OUT 34.6.10.5 STALL 34.6.11 Speed Identification 34.6.12 USB V2.0 High Speed Global Interrupt 34.6.13 Endpoint Interrupts 34.6.14 Power Modes 34.6.14.1 Controlling Device States 34.6.14.2 Not Powered State 34.6.14.3 Entering Attached State 34.6.14.4 From Powered State to Default State (Reset) 34.6.14.5 From Default State to Address State (Address Assigned) 34.6.14.6 From Address State to Configured State (Device Configured) 34.6.14.7 Entering Suspend State (Bus Activity) 34.6.14.8 Receiving a Host Resume 34.6.14.9 Sending an External Resume 34.6.15 Test Mode 34.7 USB High Speed Device Port (UDPHS) User Interface 34.7.1 UDPHS Control Register 34.7.2 UDPHS Frame Number Register 34.7.3 UDPHS Interrupt Enable Register 34.7.4 UDPHS Interrupt Status Register 34.7.5 UDPHS Clear Interrupt Register 34.7.6 UDPHS Endpoints Reset Register 34.7.7 UDPHS Test Register 34.7.8 UDPHS Endpoint Configuration Register 34.7.9 UDPHS Endpoint Control Enable Register (Control, Bulk, Interrupt Endpoints) 34.7.10 UDPHS Endpoint Control Enable Register (Isochronous Endpoints) 34.7.11 UDPHS Endpoint Control Disable Register (Control, Bulk, Interrupt Endpoints) 34.7.12 UDPHS Endpoint Control Disable Register (Isochronous Endpoint) 34.7.13 UDPHS Endpoint Control Register (Control, Bulk, Interrupt Endpoints) 34.7.14 UDPHS Endpoint Control Register (Isochronous Endpoint) 34.7.15 UDPHS Endpoint Set Status Register (Control, Bulk, Interrupt Endpoints) 34.7.16 UDPHS Endpoint Set Status Register (Isochronous Endpoint) 34.7.17 UDPHS Endpoint Clear Status Register (Control, Bulk, Interrupt Endpoints) 34.7.18 UDPHS Endpoint Clear Status Register (Isochronous Endpoint) 34.7.19 UDPHS Endpoint Status Register (Control, Bulk, Interrupt Endpoints) 34.7.20 UDPHS Endpoint Status Register (Isochronous Endpoint) 34.7.21 UDPHS DMA Channel Transfer Descriptor 34.7.22 UDPHS DMA Next Descriptor Address Register 34.7.23 UDPHS DMA Channel Address Register 34.7.24 UDPHS DMA Channel Control Register 34.7.25 UDPHS DMA Channel Status Register 35. USB Host High Speed Port (UHPHS) 35.1 Description 35.2 Embedded Characteristics 35.3 Block Diagram 35.4 Typical Connection 35.5 Product Dependencies 35.5.1 I/O Lines 35.5.2 Power Management 35.5.3 Interrupt Sources 35.6 Functional Description 35.6.1 UTMI Transceivers Sharing 35.6.2 EHCI 35.6.3 OHCI 35.7 USB Host High Speed Port (UHPHS) User Interface 35.7.1 UHPHS Host Controller Capability Register 35.7.2 UHPHS Host Controller Structural Parameters Register 35.7.3 UHPHS Host Controller Capability Parameters Register 35.7.4 UHPHS USB Command Register 35.7.5 UHPHS USB Status Register 35.7.6 UHPHS USB Interrupt Enable Register 35.7.7 UHPHS USB Frame Index Register 35.7.8 UHPHS Control Data Structure Segment Register 35.7.9 UHPHS Periodic Frame List Base Address Register 35.7.10 UHPHS Asynchronous List Address Register 35.7.11 UHPHS Configure Flag Register 35.7.12 UHPHS Port Status and Control Register 35.7.13 EHCI: REG00 - Programmable Microframe Base Value 35.7.14 EHCI: REG01 - Programmable Packet Buffer OUT/IN Thresholds 35.7.15 EHCI: REG02 - Programmable Packet Buffer Depth 35.7.16 EHCI: REG03 35.7.17 EHCI: REG04 35.7.18 EHCI: REG05 - UTMI Configuration 35.7.19 EHCI: REG06 - AHB Error Status 35.7.20 EHCI: REG07 - AHB Master Error Address 35.7.21 EHCI: REG08 - HSIC Enable/Disable 36. Gigabit Ethernet MAC (GMAC) 36.1 Description 36.2 Embedded Characteristics 36.3 Block Diagram 36.4 Signal Interface 36.5 Product Dependencies 36.5.1 I/O Lines 36.5.2 Power Management 36.5.3 Interrupt Sources 36.6 Functional Description 36.6.1 Media Access Controller 36.6.2 1588 Timestamp Unit 36.6.3 AHB Direct Memory Access Interface 36.6.3.1 Packet Buffer DMA 36.6.3.2 Partial Store and Forward Using Packet Buffer DMA 36.6.3.3 Receive AHB Buffers 36.6.3.4 Transmit AHB Buffers 36.6.3.5 DMA Bursting on the AHB 36.6.3.6 DMA Packet Buffer 36.6.3.7 Transmit Packet Buffer 36.6.3.8 Receive Packet Buffer 36.6.4 MAC Transmit Block 36.6.5 MAC Receive Block 36.6.6 Checksum Offload for IP, TCP and UDP 36.6.6.1 Receiver Checksum Offload 36.6.6.2 Transmitter Checksum Offload 36.6.7 MAC Filtering Block 36.6.8 Broadcast Address 36.6.9 Hash Addressing 36.6.10 Copy all Frames (Promiscuous Mode) 36.6.11 Disable Copy of Pause Frames 36.6.12 VLAN Support 36.6.13 Wake on LAN Support 36.6.14 IEEE 1588 Support 36.6.15 Timestamp Unit 36.6.16 MAC 802.3 Pause Frame Support 36.6.16.1 802.3 Pause Frame Reception 36.6.16.2 802.3 Pause Frame Transmission 36.6.17 MAC PFC Priority-based Pause Frame Support 36.6.17.1 PFC Pause Frame Reception 36.6.17.2 PFC Pause Frame Transmission 36.6.18 PHY Interface 36.6.19 10/100/1000 Operation 36.6.20 Jumbo Frames 36.7 Programming Interface 36.7.1 Initialization 36.7.1.1 Configuration 36.7.1.2 Receive Buffer List 36.7.1.3 Transmit Buffer List 36.7.1.4 Address Matching 36.7.1.5 PHY Maintenance 36.7.1.6 Interrupts 36.7.1.7 Transmitting Frames 36.7.1.8 Receiving Frames 36.8 Statistics Registers 36.9 Gigabit Ethernet MAC (GMAC) User Interface 36.9.1 GMAC Network Control Register 36.9.2 GMAC Network Configuration Register 36.9.3 GMAC Network Status Register 36.9.4 GMAC User Register 36.9.5 GMAC DMA Configuration Register 36.9.6 GMAC Transmit Status Register 36.9.7 GMAC Receive Buffer Queue Base Address Register 36.9.8 GMAC Transmit Buffer Queue Base Address Register 36.9.9 GMAC Receive Status Register 36.9.10 GMAC Interrupt Status Register 36.9.11 GMAC Interrupt Enable Register 36.9.12 GMAC Interrupt Disable Register 36.9.13 GMAC Interrupt Mask Register 36.9.14 GMAC PHY Maintenance Register 36.9.15 GMAC Receive Pause Quantum Register 36.9.16 GMAC Transmit Pause Quantum Register 36.9.17 GMAC TX Partial Store and Forward Register 36.9.18 GMAC RX Partial Store and Forward Register 36.9.19 GMAC RX Jumbo Frame Max Length Register 36.9.20 GMAC Hash Register Bottom 36.9.21 GMAC Hash Register Top 36.9.22 GMAC Specific Address 1 Bottom Register 36.9.23 GMAC Specific Address 1 Top Register 36.9.24 GMAC Specific Address 2 Bottom Register 36.9.25 GMAC Specific Address 2 Top Register 36.9.26 GMAC Specific Address 3 Bottom Register 36.9.27 GMAC Specific Address 3 Top Register 36.9.28 GMAC Specific Address 4 Bottom Register 36.9.29 GMAC Specific Address 4 Top Register 36.9.30 GMAC Type ID Match 1 Register 36.9.31 GMAC Type ID Match 2 Register 36.9.32 GMAC Type ID Match 3 Register 36.9.33 GMAC Type ID Match 4 Register 36.9.34 GMAC Wake on LAN Register 36.9.35 GMAC IPG Stretch Register 36.9.36 GMAC Stacked VLAN Register 36.9.37 GMAC Transmit PFC Pause Register 36.9.38 GMAC Specific Address 1 Mask Bottom Register 36.9.39 GMAC Specific Address Mask 1 Top Register 36.9.40 GMAC 1588 Timer Nanosecond Comparison Register 36.9.41 GMAC 1588 Timer Second Comparison Low Register 36.9.42 GMAC 1588 Timer Second Comparison High Register 36.9.43 GMAC PTP Event Frame Transmitted Seconds High Register 36.9.44 GMAC PTP Event Frame Received Seconds High Register 36.9.45 GMAC PTP Peer Event Frame Transmitted Seconds High Register 36.9.46 GMAC PTP Peer Event Frame Received Seconds High Register 36.9.47 GMAC Octets Transmitted Low Register 36.9.48 GMAC Octets Transmitted High Register 36.9.49 GMAC Frames Transmitted Register 36.9.50 GMAC Broadcast Frames Transmitted Register 36.9.51 GMAC Multicast Frames Transmitted Register 36.9.52 GMAC Pause Frames Transmitted Register 36.9.53 GMAC 64 Byte Frames Transmitted Register 36.9.54 GMAC 65 to 127 Byte Frames Transmitted Register 36.9.55 GMAC 128 to 255 Byte Frames Transmitted Register 36.9.56 GMAC 256 to 511 Byte Frames Transmitted Register 36.9.57 GMAC 512 to 1023 Byte Frames Transmitted Register 36.9.58 GMAC 1024 to 1518 Byte Frames Transmitted Register 36.9.59 GMAC Greater Than 1518 Byte Frames Transmitted Register 36.9.60 GMAC Transmit Underruns Register 36.9.61 GMAC Single Collision Frames Register 36.9.62 GMAC Multiple Collision Frames Register 36.9.63 GMAC Excessive Collisions Register 36.9.64 GMAC Late Collisions Register 36.9.65 GMAC Deferred Transmission Frames Register 36.9.66 GMAC Carrier Sense Errors Register 36.9.67 GMAC Octets Received Low Register 36.9.68 GMAC Octets Received High Register 36.9.69 GMAC Frames Received Register 36.9.70 GMAC Broadcast Frames Received Register 36.9.71 GMAC Multicast Frames Received Register 36.9.72 GMAC Pause Frames Received Register 36.9.73 GMAC 64 Byte Frames Received Register 36.9.74 GMAC 65 to 127 Byte Frames Received Register 36.9.75 GMAC 128 to 255 Byte Frames Received Register 36.9.76 GMAC 256 to 511 Byte Frames Received Register 36.9.77 GMAC 512 to 1023 Byte Frames Received Register 36.9.78 GMAC 1024 to 1518 Byte Frames Received Register 36.9.79 GMAC 1519 to Maximum Byte Frames Received Register 36.9.80 GMAC Undersized Frames Received Register 36.9.81 GMAC Oversized Frames Received Register 36.9.82 GMAC Jabbers Received Register 36.9.83 GMAC Frame Check Sequence Errors Register 36.9.84 GMAC Length Field Frame Errors Register 36.9.85 GMAC Receive Symbol Errors Register 36.9.86 GMAC Alignment Errors Register 36.9.87 GMAC Receive Resource Errors Register 36.9.88 GMAC Receive Overruns Register 36.9.89 GMAC IP Header Checksum Errors Register 36.9.90 GMAC TCP Checksum Errors Register 36.9.91 GMAC UDP Checksum Errors Register 36.9.92 GMAC 1588 Timer Increment Sub-nanoseconds Register 36.9.93 GMAC 1588 Timer Seconds High Register 36.9.94 GMAC 1588 Timer Seconds Low Register 36.9.95 GMAC 1588 Timer Nanoseconds Register 36.9.96 GMAC 1588 Timer Adjust Register 36.9.97 GMAC 1588 Timer Increment Register 36.9.98 GMAC PTP Event Frame Transmitted Seconds Low Register 36.9.99 GMAC PTP Event Frame Transmitted Nanoseconds Register 36.9.100 GMAC PTP Event Frame Received Seconds Low Register 36.9.101 GMAC PTP Event Frame Received Nanoseconds Register 36.9.102 GMAC PTP Peer Event Frame Transmitted Seconds Low Register 36.9.103 GMAC PTP Peer Event Frame Transmitted Nanoseconds Register 36.9.104 GMAC PTP Peer Event Frame Received Seconds Low Register 36.9.105 GMAC PTP Peer Event Frame Received Nanoseconds Register 37. Ethernet 10/100 MAC (EMAC) 37.1 Description 37.2 Embedded Characteristics 37.3 Block Diagram 37.4 Functional Description 37.4.1 Clock 37.4.2 Memory Interface 37.4.2.1 FIFO 37.4.2.2 Receive Buffers 37.4.2.3 Transmit Buffer 37.4.3 Transmit Block 37.4.4 Pause Frame Support 37.4.5 Receive Block 37.4.6 Address Checking Block 37.4.7 Broadcast Address 37.4.8 Hash Addressing 37.4.9 Copy All Frames (or Promiscuous Mode) 37.4.10 Type ID Checking 37.4.11 VLAN Support 37.4.12 Wake-on-LAN Support 37.4.13 PHY Maintenance 37.4.14 Physical Interface 37.4.14.1 RMII Transmit and Receive Operation 37.5 Programming Interface 37.5.1 Initialization 37.5.1.1 Configuration 37.5.1.2 Receive Buffer List 37.5.1.3 Transmit Buffer List 37.5.1.4 Address Matching 37.5.1.5 Interrupts 37.5.1.6 Transmitting Frames 37.5.1.7 Receiving Frames 37.6 Ethernet MAC 10/100 (EMAC) User Interface 37.6.1 Network Control Register 37.6.2 Network Configuration Register 37.6.3 Network Status Register 37.6.4 Transmit Status Register 37.6.5 Receive Buffer Queue Pointer Register 37.6.6 Transmit Buffer Queue Pointer Register 37.6.7 Receive Status Register 37.6.8 Interrupt Status Register 37.6.9 Interrupt Enable Register 37.6.10 Interrupt Disable Register 37.6.11 Interrupt Mask Register 37.6.12 PHY Maintenance Register 37.6.13 Pause Time Register 37.6.14 Hash Register Bottom 37.6.15 Hash Register Top 37.6.16 Specific Address 1 Bottom Register 37.6.17 Specific Address 1 Top Register 37.6.18 Specific Address 2 Bottom Register 37.6.19 Specific Address 2 Top Register 37.6.20 Specific Address 3 Bottom Register 37.6.21 Specific Address 3 Top Register 37.6.22 Specific Address 4 Bottom Register 37.6.23 Specific Address 4 Top Register 37.6.24 Type ID Checking Register 37.6.25 User Input/Output Register 37.6.26 Wake-on-LAN Register 37.6.27 EMAC Statistics Registers 37.6.27.1 Pause Frames Received Register 37.6.27.2 Frames Transmitted OK Register 37.6.27.3 Single Collision Frames Register 37.6.27.4 Multicollision Frames Register 37.6.27.5 Frames Received OK Register 37.6.27.6 Frames Check Sequence Errors Register 37.6.27.7 Alignment Errors Register 37.6.27.8 Deferred Transmission Frames Register 37.6.27.9 Late Collisions Register 37.6.27.10 Excessive Collisions Register 37.6.27.11 Transmit Underrun Errors Register 37.6.27.12 Carrier Sense Errors Register 37.6.27.13 Receive Resource Errors Register 37.6.27.14 Receive Overrun Errors Register 37.6.27.15 Receive Symbol Errors Register 37.6.27.16 Excessive Length Errors Register 37.6.27.17 Receive Jabbers Register 37.6.27.18 Undersize Frames Register 37.6.27.19 SQE Test Errors Register 37.6.27.20 Received Length Field Mismatch Register 38. High Speed Multimedia Card Interface (HSMCI) 38.1 Description 38.2 Embedded Characteristics 38.3 Block Diagram 38.4 Application Block Diagram 38.5 Pin Name List 38.6 Product Dependencies 38.6.1 I/O Lines 38.6.2 Power Management 38.6.3 Interrupt Sources 38.7 Bus Topology 38.8 High Speed MultiMedia Card Operations 38.8.1 Command - Response Operation 38.8.2 Data Transfer Operation 38.8.3 Read Operation 38.8.4 Write Operation 38.8.5 WRITE_SINGLE_BLOCK Operation using DMA Controller 38.8.6 READ_SINGLE_BLOCK Operation using DMA Controller 38.8.6.1 Block Length is Multiple of 4 38.8.6.2 Block Length is Not Multiple of 4 and Padding Not Used (HSMCI_DMA.ROPT = 0) 38.8.6.3 Block Length is Not Multiple of 4, with Padding Value (HSMCI_DMA.ROPT = 1) 38.8.7 WRITE_MULTIPLE_BLOCK 38.8.7.1 One Block per Descriptor 38.8.8 READ_MULTIPLE_BLOCK 38.8.8.1 Block Length is a Multiple of 4 38.8.8.2 Block Length is Not Multiple of 4 (HSMCI_DMA.ROPT = 0) 38.8.8.3 Block Length is Not a Multiple of 4 (HSMCI_DMA.ROPT = 1) 38.9 SD/SDIO Card Operation 38.9.1 SDIO Data Transfer Type 38.9.2 SDIO Interrupts 38.10 CE-ATA Operation 38.10.1 Executing an ATA Polling Command 38.10.2 Executing an ATA Interrupt Command 38.10.3 Aborting an ATA Command 38.10.4 CE-ATA Error Recovery 38.11 HSMCI Boot Operation Mode 38.11.1 Boot Procedure, Processor Mode 38.11.2 Boot Procedure DMA Mode 38.12 HSMCI Transfer Done Timings 38.12.1 Definition 38.12.2 Read Access 38.12.3 Write Access 38.13 Register Write Protection 38.14 High Speed MultiMedia Card Interface (HSMCI) User Interface 38.14.1 HSMCI Control Register 38.14.2 HSMCI Mode Register 38.14.3 HSMCI Data Timeout Register 38.14.4 HSMCI SDCard/SDIO Register 38.14.5 HSMCI Argument Register 38.14.6 HSMCI Command Register 38.14.7 HSMCI Block Register 38.14.8 HSMCI Completion Signal Timeout Register 38.14.9 HSMCI Response Register 38.14.10 HSMCI Receive Data Register 38.14.11 HSMCI Transmit Data Register 38.14.12 HSMCI Status Register 38.14.13 HSMCI Interrupt Enable Register 38.14.14 HSMCI Interrupt Disable Register 38.14.15 HSMCI Interrupt Mask Register 38.14.16 HSMCI DMA Configuration Register 38.14.17 HSMCI Configuration Register 38.14.18 HSMCI Write Protection Mode Register 38.14.19 HSMCI Write Protection Status Register 38.14.20 HSMCI FIFOx Memory Aperture 39. Serial Peripheral Interface (SPI) 39.1 Description 39.2 Embedded Characteristics 39.3 Block Diagram 39.4 Application Block Diagram 39.5 Signal Description 39.6 Product Dependencies 39.6.1 I/O Lines 39.6.2 Power Management 39.6.3 Interrupt 39.6.4 Direct Memory Access Controller (DMAC) 39.7 Functional Description 39.7.1 Modes of Operation 39.7.2 Data Transfer 39.7.3 Master Mode Operations 39.7.3.1 Master Mode Block Diagram 39.7.3.2 Master Mode Flow Diagram 39.7.3.3 Clock Generation 39.7.3.4 Transfer Delays 39.7.3.5 Peripheral Selection 39.7.3.6 SPI Direct Access Memory Controller (DMAC) 39.7.3.7 Peripheral Chip Select Decoding 39.7.3.8 Peripheral Deselection without DMA 39.7.3.9 Peripheral Deselection with DMA 39.7.3.10 Mode Fault Detection 39.7.4 SPI Slave Mode 39.7.5 Register Write Protection 39.8 Serial Peripheral Interface (SPI) User Interface 39.8.1 SPI Control Register 39.8.2 SPI Mode Register 39.8.3 SPI Receive Data Register 39.8.4 SPI Transmit Data Register 39.8.5 SPI Status Register 39.8.6 SPI Interrupt Enable Register 39.8.7 SPI Interrupt Disable Register 39.8.8 SPI Interrupt Mask Register 39.8.9 SPI Chip Select Register 39.8.10 SPI Write Protection Mode Register 39.8.11 SPI Write Protection Status Register 40. Two-wire Interface (TWI) 40.1 Description 40.2 Embedded Characteristics 40.3 List of Abbreviations 40.4 Block Diagram 40.5 I/O Lines Description 40.6 Product Dependencies 40.6.1 I/O Lines 40.6.2 Power Management 40.6.3 Interrupt Sources 40.7 Functional Description 40.7.1 Transfer Format 40.7.2 Modes of Operation 40.7.3 Master Mode 40.7.3.1 Definition 40.7.3.2 Programming Master Mode 40.7.3.3 Master Transmitter Mode 40.7.3.4 Master Receiver Mode 40.7.3.5 Internal Address 40.7.3.6 Using the DMA Controller 40.7.3.7 SMBus Quick Command (Master Mode Only) 40.7.3.8 Read/Write Flowcharts 40.7.4 Multi-master Mode 40.7.4.1 Definition 40.7.4.2 Two Multi-master Modes 40.7.5 Slave Mode 40.7.5.1 Definition 40.7.5.2 Programming Slave Mode 40.7.5.3 Receiving Data 40.7.5.4 Data Transfer 40.7.5.5 Using the DMA Controller 40.7.5.6 Read Write Flowcharts 40.7.6 Register Write Protection 40.8 Two-wire Interface (TWI) User Interface 40.8.1 TWI Control Register 40.8.2 TWI Master Mode Register 40.8.3 TWI Slave Mode Register 40.8.4 TWI Internal Address Register 40.8.5 TWI Clock Waveform Generator Register 40.8.6 TWI Status Register 40.8.7 TWI Interrupt Enable Register 40.8.8 TWI Interrupt Disable Register 40.8.9 TWI Interrupt Mask Register 40.8.10 TWI Receive Holding Register 40.8.11 TWI Transmit Holding Register 40.8.12 TWI Write Protection Mode Register 40.8.13 TWI Write Protection Status Register 41. Synchronous Serial Controller (SSC) 41.1 Description 41.2 Embedded Characteristics 41.3 Block Diagram 41.4 Application Block Diagram 41.5 SSC Application Examples 41.6 Pin Name List 41.7 Product Dependencies 41.7.1 I/O Lines 41.7.2 Power Management 41.7.3 Interrupt 41.8 Functional Description 41.8.1 Clock Management 41.8.1.1 Clock Divider 41.8.1.2 Transmitter Clock Management 41.8.1.3 Receiver Clock Management 41.8.1.4 Serial Clock Ratio Considerations 41.8.2 Transmitter Operations 41.8.3 Receiver Operations 41.8.4 Start 41.8.5 Frame Sync 41.8.5.1 Frame Sync Data 41.8.5.2 Frame Sync Edge Detection 41.8.6 Receive Compare Modes 41.8.6.1 Compare Functions 41.8.7 Data Format 41.8.8 Loop Mode 41.8.9 Interrupt 41.8.10 Register Write Protection 41.9 Synchronous Serial Controller (SSC) User Interface 41.9.1 SSC Control Register 41.9.2 SSC Clock Mode Register 41.9.3 SSC Receive Clock Mode Register 41.9.4 SSC Receive Frame Mode Register 41.9.5 SSC Transmit Clock Mode Register 41.9.6 SSC Transmit Frame Mode Register 41.9.7 SSC Receive Holding Register 41.9.8 SSC Transmit Holding Register 41.9.9 SSC Receive Synchronization Holding Register 41.9.10 SSC Transmit Synchronization Holding Register 41.9.11 SSC Receive Compare 0 Register 41.9.12 SSC Receive Compare 1 Register 41.9.13 SSC Status Register 41.9.14 SSC Interrupt Enable Register 41.9.15 SSC Interrupt Disable Register 41.9.16 SSC Interrupt Mask Register 41.9.17 SSC Write Protection Mode Register 41.9.18 SSC Write Protection Status Register 42. Debug Unit (DBGU) 42.1 Description 42.2 Embedded Characteristics 42.3 Block Diagram 42.4 Product Dependencies 42.4.1 I/O Lines 42.4.2 Power Management 42.4.3 Interrupt Source 42.5 UART Operations 42.5.1 Baud Rate Generator 42.5.2 Receiver 42.5.2.1 Receiver Reset, Enable and Disable 42.5.2.2 Start Detection and Data Sampling 42.5.2.3 Receiver Ready 42.5.2.4 Receiver Overrun 42.5.2.5 Parity Error 42.5.2.6 Receiver Framing Error 42.5.3 Transmitter 42.5.3.1 Transmitter Reset, Enable and Disable 42.5.3.2 Transmit Format 42.5.3.3 Transmitter Control 42.5.4 DMA Support 42.5.5 Test Modes 42.5.6 Debug Communication Channel Support 42.5.7 Chip Identifier 42.5.8 ICE Access Prevention 42.6 Debug Unit (DBGU) User Interface 42.6.1 Debug Unit Control Register 42.6.2 Debug Unit Mode Register 42.6.3 Debug Unit Interrupt Enable Register 42.6.4 Debug Unit Interrupt Disable Register 42.6.5 Debug Unit Interrupt Mask Register 42.6.6 Debug Unit Status Register 42.6.7 Debug Unit Receive Holding Register 42.6.8 Debug Unit Transmit Holding Register 42.6.9 Debug Unit Baud Rate Generator Register 42.6.10 Debug Unit Chip ID Register 42.6.11 Debug Unit Chip ID Extension Register 42.6.12 Debug Unit Force NTRST Register 43. Universal Asynchronous Receiver Transmitter (UART) 43.1 Description 43.2 Embedded Characteristics 43.3 Block Diagram 43.4 Product Dependencies 43.4.1 I/O Lines 43.4.2 Power Management 43.4.3 Interrupt Sources 43.5 Functional Description 43.5.1 Baud Rate Generator 43.5.2 Receiver 43.5.2.1 Receiver Reset, Enable and Disable 43.5.2.2 Start Detection and Data Sampling 43.5.2.3 Receiver Ready 43.5.2.4 Receiver Overrun 43.5.2.5 Parity Error 43.5.2.6 Receiver Framing Error 43.5.3 Transmitter 43.5.3.1 Transmitter Reset, Enable and Disable 43.5.3.2 Transmit Format 43.5.3.3 Transmitter Control 43.5.4 DMA Support 43.5.5 Test Modes 43.6 Universal Asynchronous Receiver Transmitter (UART) User Interface 43.6.1 UART Control Register 43.6.2 UART Mode Register 43.6.3 UART Interrupt Enable Register 43.6.4 UART Interrupt Disable Register 43.6.5 UART Interrupt Mask Register 43.6.6 UART Status Register 43.6.7 UART Receiver Holding Register 43.6.8 UART Transmit Holding Register 43.6.9 UART Baud Rate Generator Register 44. Universal Synchronous Asynchronous Receiver Transmitter (USART) 44.1 Description 44.2 Embedded Characteristics 44.3 Block Diagram 44.4 I/O Lines Description 44.5 Product Dependencies 44.5.1 I/O Lines 44.5.2 Power Management 44.5.3 Interrupt Sources 44.6 Functional Description 44.6.1 Baud Rate Generator 44.6.1.1 Baud Rate in Asynchronous Mode 44.6.1.2 Fractional Baud Rate in Asynchronous Mode 44.6.1.3 Baud Rate in Synchronous Mode or SPI Mode 44.6.1.4 Baud Rate in ISO 7816 Mode 44.6.2 Receiver and Transmitter Control 44.6.3 Synchronous and Asynchronous Modes 44.6.3.1 Transmitter Operations 44.6.3.2 Manchester Encoder 44.6.3.3 Asynchronous Receiver 44.6.3.4 Manchester Decoder 44.6.3.5 Radio Interface: Manchester Encoded USART Application 44.6.3.6 Synchronous Receiver 44.6.3.7 Receiver Operations 44.6.3.8 Parity 44.6.3.9 Multidrop Mode 44.6.3.10 Transmitter Timeguard 44.6.3.11 Receiver Time-out 44.6.3.12 Framing Error 44.6.3.13 Transmit Break 44.6.3.14 Receive Break 44.6.3.15 Hardware Handshaking 44.6.4 ISO7816 Mode 44.6.4.1 ISO7816 Mode Overview 44.6.4.2 Protocol T = 0 44.6.4.3 Protocol T = 1 44.6.5 IrDA Mode 44.6.5.1 IrDA Modulation 44.6.5.2 IrDA Baud Rate 44.6.5.3 IrDA Demodulator 44.6.6 RS485 Mode 44.6.7 SPI Mode 44.6.7.1 Modes of Operation 44.6.7.2 Baud Rate 44.6.7.3 Data Transfer 44.6.7.4 Receiver and Transmitter Control 44.6.7.5 Character Transmission 44.6.7.6 Character Reception 44.6.7.7 Receiver Timeout 44.6.8 Test Modes 44.6.8.1 Normal Mode 44.6.8.2 Automatic Echo Mode 44.6.8.3 Local Loopback Mode 44.6.8.4 Remote Loopback Mode 44.6.9 Register Write Protection 44.7 Universal Synchronous Asynchronous Receiver Transmitter (USART) User Interface 44.7.1 USART Control Register 44.7.2 USART Control Register (SPI_MODE) 44.7.3 USART Mode Register 44.7.4 USART Mode Register (SPI_MODE) 44.7.5 USART Interrupt Enable Register 44.7.6 USART Interrupt Enable Register (SPI_MODE) 44.7.7 USART Interrupt Disable Register 44.7.8 USART Interrupt Disable Register (SPI_MODE) 44.7.9 USART Interrupt Mask Register 44.7.10 USART Interrupt Mask Register (SPI_MODE) 44.7.11 USART Channel Status Register 44.7.12 USART Channel Status Register (SPI_MODE) 44.7.13 USART Receive Holding Register 44.7.14 USART Transmit Holding Register 44.7.15 USART Baud Rate Generator Register 44.7.16 USART Receiver Time-out Register 44.7.17 USART Transmitter Timeguard Register 44.7.18 USART FI DI RATIO Register 44.7.19 USART Number of Errors Register 44.7.20 USART IrDA Filter Register 44.7.21 USART Manchester Configuration Register 44.7.22 USART Write Protection Mode Register 44.7.23 USART Write Protection Status Register 45. CAN Controller 45.1 Description 45.2 Embedded Characteristics 45.3 Block Diagram 45.4 Application Block Diagram 45.5 I/O Lines Description 45.6 Product Dependencies 45.6.1 I/O Lines 45.6.2 Power Management 45.6.3 Interrupt Sources 45.7 CAN Controller Features 45.7.1 CAN Protocol Overview 45.7.2 Mailbox Organization 45.7.2.1 Message Acceptance Procedure 45.7.2.2 Receive Mailbox 45.7.2.3 Transmit Mailbox 45.7.3 Time Management Unit 45.7.4 CAN 2.0 Standard Features 45.7.4.1 CAN Bit Timing Configuration 45.7.4.2 Error Detection 45.7.4.3 Overload 45.7.5 Low-power Mode 45.7.5.1 Enabling Low-power Mode 45.7.5.2 Disabling Low-power Mode 45.8 Functional Description 45.8.1 CAN Controller Initialization 45.8.2 CAN Controller Interrupt Handling 45.8.3 CAN Controller Message Handling 45.8.3.1 Receive Handling 45.8.3.2 Transmission Handling 45.8.3.3 Remote Frame Handling 45.8.4 CAN Controller Timing Modes 45.8.4.1 Timestamping Mode 45.8.4.2 Time Triggered Mode 45.8.5 Register Write Protection 45.9 Controller Area Network (CAN) User Interface 45.9.1 CAN Mode Register 45.9.2 CAN Interrupt Enable Register 45.9.3 CAN Interrupt Disable Register 45.9.4 CAN Interrupt Mask Register 45.9.5 CAN Status Register 45.9.6 CAN Baudrate Register 45.9.7 CAN Timer Register 45.9.8 CAN Timestamp Register 45.9.9 CAN Error Counter Register 45.9.10 CAN Transfer Command Register 45.9.11 CAN Abort Command Register 45.9.12 CAN Write Protection Mode Register 45.9.13 CAN Write Protection Status Register 45.9.14 CAN Message Mode Register 45.9.15 CAN Message Acceptance Mask Register 45.9.16 CAN Message ID Register 45.9.17 CAN Message Family ID Register 45.9.18 CAN Message Status Register 45.9.19 CAN Message Data Low Register 45.9.20 CAN Message Data High Register 45.9.21 CAN Message Control Register 46. Software Modem Device (SMD) 46.1 Description 46.2 Embedded Characteristics 46.3 Block Diagram 46.4 Software Modem Device (SMD) User Interface 46.4.1 SMD Drive Register 47. Timer Counter (TC) 47.1 Description 47.2 Embedded Characteristics 47.3 Block Diagram 47.4 Pin List 47.5 Product Dependencies 47.5.1 I/O Lines 47.5.2 Power Management 47.5.3 Interrupt Sources 47.5.4 Fault Output 47.6 Functional Description 47.6.1 Description 47.6.2 32-bit Counter 47.6.3 Clock Selection 47.6.4 Clock Control 47.6.5 Operating Modes 47.6.6 Trigger 47.6.7 Capture Mode 47.6.8 Capture Registers A and B 47.6.9 Trigger Conditions 47.6.10 Waveform Mode 47.6.11 Waveform Selection 47.6.11.1 WAVSEL = 00 47.6.11.2 WAVSEL = 10 47.6.11.3 WAVSEL = 01 47.6.11.4 WAVSEL = 11 47.6.12 External Event/Trigger Conditions 47.6.13 Output Controller 47.6.14 2-bit Gray Up/Down Counter for Stepper Motor 47.6.15 Fault Mode 47.6.16 Register Write Protection 47.7 Timer Counter (TC) User Interface 47.7.1 TC Channel Control Register 47.7.2 TC Channel Mode Register: Capture Mode 47.7.3 TC Channel Mode Register: Waveform Mode 47.7.4 TC Stepper Motor Mode Register 47.7.5 TC Counter Value Register 47.7.6 TC Register A 47.7.7 TC Register B 47.7.8 TC Register C 47.7.9 TC Status Register 47.7.10 TC Interrupt Enable Register 47.7.11 TC Interrupt Disable Register 47.7.12 TC Interrupt Mask Register 47.7.13 TC Block Control Register 47.7.14 TC Block Mode Register 47.7.15 TC Fault Mode Register 47.7.16 TC Write Protection Mode Register 48. Pulse Width Modulation Controller (PWM) 48.1 Description 48.2 Embedded Characteristics 48.3 Block Diagram 48.4 I/O Lines Description 48.5 Product Dependencies 48.5.1 I/O Lines 48.5.2 Power Management 48.5.3 Interrupt Sources 48.5.4 Fault Inputs 48.6 Functional Description 48.6.1 PWM Clock Generator 48.6.2 PWM Channel 48.6.2.1 Channel Block Diagram 48.6.2.2 Comparator 48.6.2.3 2-bit Gray Up/Down Counter for Stepper Motor 48.6.2.4 Dead-Time Generator 48.6.2.5 Output Override 48.6.2.6 Fault Protection 48.6.2.7 Synchronous Channels 48.6.3 PWM Comparison Units 48.6.4 PWM Event Lines 48.6.5 PWM Controller Operations 48.6.5.1 Initialization 48.6.5.2 Source Clock Selection Criteria 48.6.5.3 Changing the Duty-Cycle, the Period and the Dead-Times 48.6.5.4 Changing the Update Period of Synchronous Channels 48.6.5.5 Changing the Comparison Value and the Comparison Configuration 48.6.5.6 Interrupt Sources 48.6.6 Register Write Protection 48.7 Pulse Width Modulation Controller (PWM) User Interface 48.7.1 PWM Clock Register 48.7.2 PWM Enable Register 48.7.3 PWM Disable Register 48.7.4 PWM Status Register 48.7.5 PWM Interrupt Enable Register 1 48.7.6 PWM Interrupt Disable Register 1 48.7.7 PWM Interrupt Mask Register 1 48.7.8 PWM Interrupt Status Register 1 48.7.9 PWM Sync Channels Mode Register 48.7.10 PWM Sync Channels Update Control Register 48.7.11 PWM Sync Channels Update Period Register 48.7.12 PWM Sync Channels Update Period Update Register 48.7.13 PWM Interrupt Enable Register 2 48.7.14 PWM Interrupt Disable Register 2 48.7.15 PWM Interrupt Mask Register 2 48.7.16 PWM Interrupt Status Register 2 48.7.17 PWM Output Override Value Register 48.7.18 PWM Output Selection Register 48.7.19 PWM Output Selection Set Register 48.7.20 PWM Output Selection Clear Register 48.7.21 PWM Output Selection Set Update Register 48.7.22 PWM Output Selection Clear Update Register 48.7.23 PWM Fault Mode Register 48.7.24 PWM Fault Status Register 48.7.25 PWM Fault Clear Register 48.7.26 PWM Fault Protection Value Register 48.7.27 PWM Fault Protection Enable Register 48.7.28 PWM Event Line x Register 48.7.29 PWM Stepper Motor Mode Register 48.7.30 PWM Write Protection Control Register 48.7.31 PWM Write Protection Status Register 48.7.32 PWM Comparison x Value Register 48.7.33 PWM Comparison x Value Update Register 48.7.34 PWM Comparison x Mode Register 48.7.35 PWM Comparison x Mode Update Register 48.7.36 PWM Channel Mode Register 48.7.37 PWM Channel Duty Cycle Register 48.7.38 PWM Channel Duty Cycle Update Register 48.7.39 PWM Channel Period Register 48.7.40 PWM Channel Period Update Register 48.7.41 PWM Channel Counter Register 48.7.42 PWM Channel Dead Time Register 48.7.43 PWM Channel Dead Time Update Register 49. Analog-to-Digital Converter (ADC) 49.1 Description 49.2 Embedded Characteristics 49.3 Block Diagram 49.4 Signal Description 49.5 Product Dependencies 49.5.1 Power Management 49.5.2 Interrupt Sources 49.5.3 I/O Lines 49.5.4 Timer Triggers 49.5.5 PWM Event Line 49.5.6 Fault Output 49.5.7 Conversion Performances 49.6 Functional Description 49.6.1 Analog-to-Digital Conversion 49.6.2 ADC Clock 49.6.3 ADC Reference Voltage 49.6.4 Conversion Resolution 49.6.5 Conversion Results 49.6.6 Conversion Triggers 49.6.7 Sleep Mode and Conversion Sequencer 49.6.8 Comparison Window 49.6.9 Differential Inputs 49.6.10 Input Gain and Offset 49.6.11 ADC Timings 49.6.12 Automatic Calibration 49.6.13 Touchscreen 49.6.13.1 Touchscreen Mode 49.6.13.2 4-wire Resistive Touchscreen Principles 49.6.13.3 4-wire Position Measurement Method 49.6.13.4 4-wire Pressure Measurement Method 49.6.13.5 5-wire Resistive Touchscreen Principles 49.6.13.6 5-wire Position Measurement Method 49.6.13.7 Sequence and Noise Filtering 49.6.13.8 Measured Values, Registers and Flags 49.6.13.9 Pen Detect Method 49.6.14 Buffer Structure 49.6.14.1 Classical ADC Channels Only 49.6.14.2 Touchscreen Channels Only 49.6.14.3 Interleaved Channels 49.6.14.4 Pen Detection Status 49.6.15 Fault Output 49.6.16 Register Write Protection 49.7 Analog-to-Digital (ADC) User Interface 49.7.1 ADC Control Register 49.7.2 ADC Mode Register 49.7.3 ADC Channel Sequence 1 Register 49.7.4 ADC Channel Sequence 2 Register 49.7.5 ADC Channel Enable Register 49.7.6 ADC Channel Disable Register 49.7.7 ADC Channel Status Register 49.7.8 ADC Last Converted Data Register 49.7.9 ADC Interrupt Enable Register 49.7.10 ADC Interrupt Disable Register 49.7.11 ADC Interrupt Mask Register 49.7.12 ADC Interrupt Status Register 49.7.13 ADC Overrun Status Register 49.7.14 ADC Extended Mode Register 49.7.15 ADC Compare Window Register 49.7.16 ADC Channel Gain Register 49.7.17 ADC Channel Offset Register 49.7.18 ADC Channel Data Register 49.7.19 ADC Analog Control Register 49.7.20 ADC Touchscreen Mode Register 49.7.21 ADC Touchscreen X Position Register 49.7.22 ADC Touchscreen Y Position Register 49.7.23 ADC Touchscreen Pressure Register 49.7.24 ADC Trigger Register 49.7.25 ADC Write Protection Mode Register 49.7.26 ADC Write Protection Status Register 50. True Random Number Generator (TRNG) 50.1 Description 50.2 Embedded Characteristics 50.3 Block Diagram 50.4 Product Dependencies 50.4.1 Power Management 50.4.2 Interrupt Sources 50.5 Functional Description 50.6 True Random Number Generator (TRNG) User Interface 50.6.1 TRNG Control Register 50.6.2 TRNG Interrupt Enable Register 50.6.3 TRNG Interrupt Disable Register 50.6.4 TRNG Interrupt Mask Register 50.6.5 TRNG Interrupt Status Register 50.6.6 TRNG Output Data Register 51. Advanced Encryption Standard (AES) 51.1 Description 51.2 Embedded Characteristics 51.3 Product Dependencies 51.3.1 Power Management 51.3.2 Interrupt Sources 51.4 Functional Description 51.4.1 AES Register Endianness 51.4.2 Operation Modes 51.4.3 Double Input Buffer 51.4.4 Start Modes 51.4.4.1 Manual Mode 51.4.4.2 Auto Mode 51.4.4.3 DMA Mode 51.4.5 Last Output Data Mode 51.4.5.1 Manual and Auto Modes 51.4.5.2 DMA Mode 51.4.6 Security Features 51.4.6.1 Unspecified Register Access Detection 51.5 Advanced Encryption Standard (AES) User Interface 51.5.1 AES Control Register 51.5.2 AES Mode Register 51.5.3 AES Interrupt Enable Register 51.5.4 AES Interrupt Disable Register 51.5.5 AES Interrupt Mask Register 51.5.6 AES Interrupt Status Register 51.5.7 AES Key Word Register x 51.5.8 AES Input Data Register x 51.5.9 AES Output Data Register x 51.5.10 AES Initialization Vector Register x 52. Triple Data Encryption Standard (TDES) 52.1 Description 52.2 Embedded Characteristics 52.3 Product Dependencies 52.3.1 Power Management 52.3.2 Interrupt Sources 52.4 Functional Description 52.4.1 Operating Modes 52.4.2 Start Modes 52.4.2.1 Manual Mode 52.4.2.2 Auto Mode 52.4.2.3 DMA Mode 52.4.3 Last Output Data Mode 52.4.3.1 Manual and Auto Modes 52.4.3.2 DMA Mode 52.4.4 Security Features 52.4.4.1 Unspecified Register Access Detection 52.5 Triple Data Encryption Standard (TDES) User Interface 52.5.1 TDES Control Register 52.5.2 TDES Mode Register 52.5.3 TDES Interrupt Enable Register 52.5.4 TDES Interrupt Disable Register 52.5.5 TDES Interrupt Mask Register 52.5.6 TDES Interrupt Status Register 52.5.7 TDES Key 1 Word Register x 52.5.8 TDES Key 2 Word Register x 52.5.9 TDES Key 3 Word Register x 52.5.10 TDES Input Data Register x 52.5.11 TDES Output Data Register x 52.5.12 TDES Initialization Vector Register x 52.5.13 TDES XTEA Rounds Register 53. Secure Hash Algorithm (SHA) 53.1 Description 53.2 Embedded Characteristics 53.3 Product Dependencies 53.3.1 Power Management 53.3.2 Interrupt Sources 53.4 Functional Description 53.4.1 SHA Algorithm 53.4.2 Processing Period 53.4.3 Double Input Buffer 53.4.4 Start Modes 53.4.4.1 Manual Mode 53.4.4.2 Auto Mode 53.4.4.3 DMA Mode 53.4.4.4 SHA Register Endianism 53.4.5 Security Features 53.5 Secure Hash Algorithm (SHA) User Interface 53.5.1 SHA Control Register 53.5.2 SHA Mode Register 53.5.3 SHA Interrupt Enable Register 53.5.4 SHA Interrupt Disable Register 53.5.5 SHA Interrupt Mask Register 53.5.6 SHA Interrupt Status Register 53.5.7 SHA Input Data x Register 53.5.8 SHA Input/Output Data Register x 54. Electrical Characteristics 54.1 Absolute Maximum Ratings 54.2 DC Characteristics 54.3 Power Consumption 54.3.1 Static Current 54.3.2 Active Mode 54.3.3 Low-power Modes 54.3.3.1 Backup Mode 54.3.3.2 Idle Mode 54.3.3.3 Ultra Low-power Mode 54.3.3.4 Low-power Mode Summary Table 54.3.4 Power Consumption versus Modes 54.4 Clock Characteristics 54.4.1 Processor Clock Characteristics 54.4.2 Master Clock Characteristics 54.5 Main Oscillator Characteristics 54.5.1 Crystal Oscillator Characteristics 54.5.2 XIN Clock Characteristics 54.6 12 MHz RC Oscillator Characteristics 54.7 32 kHz Oscillator Characteristics 54.7.1 32 kHz Crystal Characteristics 54.7.2 XIN32 Clock Characteristics 54.8 32 kHz RC Oscillator Characteristics 54.9 PLL Characteristics 54.9.1 UTMI PLL Characteristics 54.10 USB HS Characteristics 54.10.1 USB HS Electrical Characteristics 54.10.2 USB HS Static Power Consumption 54.10.3 USB HS Dynamic Power Consumption 54.11 12-bit ADC Characteristics 54.11.1 ADC Power Supply 54.11.2 External Reference Voltage 54.11.3 ADC Timings 54.11.4 ADC Transfer Function 54.11.4.1 Differential Mode 54.11.4.2 Single-ended Mode 54.11.4.3 Example of LSB Computation 54.11.5 ADC Electrical Characteristics 54.11.5.1 Gain and Offset Errors 54.11.5.2 ADC Electrical Performances 54.11.5.3 ADC Channel Input Impedance 54.12 POR Characteristics 54.12.1 Core Power Supply POR Characteristics 54.12.2 Backup Power Supply POR Characteristics 54.13 SMC Timings 54.13.1 Timing Conditions 54.13.2 Timing Extraction 54.13.2.1 Read Timings 54.13.2.2 Write Timings 54.13.2.3 FPGA Timings 54.14 SPI Timings 54.14.1 Maximum SPI Frequency 54.14.2 SPI Timing Conditions 54.14.3 Timing Extraction 54.15 MPDDRC Timings 54.15.1 Board Design Constraints 54.15.2 DDR2-SDRAM 54.15.3 LPDDR1-SDRAM 54.15.4 LPDDR2-SDRAM 54.16 SSC Timings 54.16.1 SSC Timing Conditions 54.16.2 Timing Extraction 54.17 ISI Timings 54.17.1 ISI Timing Conditions 54.17.2 Timing Extraction 54.18 MCI Timings 54.19 EMAC/GMAC Timings 54.19.1 EMAC/GMAC Timing Conditions 54.19.2 Timing Constraints 54.19.2.1 MII Mode 54.20 USART in Asynchronous Modes 54.21 USART in SPI Mode Timings 54.21.1 USART Timing Conditions 54.21.2 Timing Extraction 54.22 Two-wire Interface Characteristics 55. Mechanical Characteristics 55.1 324-ball LFBGA Mechanical Characteristics 55.2 324-ball TFBGA Mechanical Characteristics 56. Schematic Checklist 56.1 Power Supply 56.2 Clock, Oscillator and PLL 56.3 ICE and JTAG 56.4 Reset and Test 56.5 Shutdown/Wake-up Logic 56.6 Parallel Input/Output (PIO) 56.7 Analog-to-Digital Converter (ADC) 56.8 External Bus Interface (EBI) 56.9 High-Speed MultiMedia Card Interface (HSMCI) - DDR2/LPDDR/LPDDR2 Controller - NAND Flash Support 56.10 USB High-Speed Host (UHPHS)/USB High-Speed Device (UDPHS) 56.11 EBI and DDR2/LPDDR/LPDDR2 Hardware Interface 56.12 Boot Program Hardware Constraints 57. Marking 58. Ordering Information 59. Errata 59.1 Standard Boot Strategies 59.1.1 Boot ROM: Xmodem is not working 59.1.2 Boot ROM: Boot on MCI1 is not working 59.1.3 Boot ROM: NAND Flash detection using ONFI parameters does not work 59.2 Advanced Interrupt Controller (AIC) 59.2.1 AIC: Interrupt vectoring 59.3 Watchdog Timer (WDT) 59.3.1 WDT: WDRPROC = 1 leads to unpredictible behavior 59.4 Slow Clock Controller (SCKC) 59.4.1 SCKC: OSCSEL setting does not affect Slow Clock oscillator selection 59.5 Multi-port DDR-SDRAM Controller (MPDDRC) 59.5.1 MPDDRC: LPDDR2 Refresh per bank is not working 59.5.2 MPDDRC: Self-refresh mode is not working with LPDDR1-SDRAM 59.5.3 MPDDRC: The automatic self-refresh of the DDR controller is not working 59.6 Static Memory Controller (SMC) 59.6.1 SMC: ECC Value after ERASE is not correct 59.7 DMA Controller (DMAC) 59.7.1 DMAC: Not possible to enable write protection on DMAC0 and DMAC1 59.7.2 DMAC: Not possible to transfer data with DMA to the SHA when SHA384 or SHA512 algorithm is selected 59.8 LCD Controller (LCDC) 59.8.1 LCDC: LCDC PWM is not usable with DIV_1 59.9 USB Host High Speed Port (UHPHS) 59.9.1 UHPHS: USB Host Power Consumption in EHCI Mode 59.10 Gigabit Ethernet MAC (GMAC) 59.10.1 GMAC: TX packet buffer DMA lockup when reading used status 59.10.2 GMAC: TX packet buffer DMA writeback status overflow 59.10.3 GMAC: Bad association of timestamps and PTP packets 59.11 PWM Controller (PWM) 59.11.1 PWM: Wrong counter event 59.12 Universal Synchronous Asynchronous Receiver Transmitter (USART) 59.12.1 USART: USART Framing error not detected if last data bit is 1 60. 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