Datasheet SiHH070N60EF (Vishay) - 6
| Hersteller | Vishay |
| Beschreibung | EF Series Power MOSFET With Fast Body Diode |
| Seiten / Seite | 9 / 6 — SiHH070N60EF. Fig. 18 - Basic Gate Charge Waveform. Fig. 19 - Gate Charge … |
| Dateiformat / Größe | PDF / 184 Kb |
| Dokumentensprache | Englisch |
SiHH070N60EF. Fig. 18 - Basic Gate Charge Waveform. Fig. 19 - Gate Charge Test Circuit
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SiHH070N60EF
www.vishay.com Vishay Siliconix Current regulator Same type as D.U.T. Qg 10 V 50 kΩ Q Q 12 V 0.2 μF gs gd 0.3 μF + V V D.U.T. DS - G VGS Charge 3 mA
Fig. 18 - Basic Gate Charge Waveform
I I G D Current sampling resistors
Fig. 19 - Gate Charge Test Circuit Peak Diode Recovery dv/dt Test Circuit
+ Circuit layout considerations D.U.T. • Low stray inductance 3 • Ground plane • Low leakage inductance current transformer - + 2 - 4 + - 1 Rg • dv/dt controlled by R + g • Driver same type as D.U.T. V - DD • ISD controlled by duty factor “D” • D.U.T. - device under test 1 Driver gate drive P.W. Period D = P.W. Period VGS = 10 V a D.U.T. ISD waveform 2 Reverse recovery Body diode forward current current di/dt 3 D.U.T. V waveform DS Diode recovery dv/dt VDD Re-applied voltage Body diode forward drop Inductor current 4 Ripple ≤ 5 % ISD
Note
a. V = 5 V for logic level devices GS
Fig. 20 - For N-Channel
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package / tape drawings, part marking, and reliability data, see www.vishay.com/ppg?92290. S20-0109-Rev. B, 02-Mar-2020
6
Document Number: 92290 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
www.vishay.com Vishay Siliconix Current regulator Same type as D.U.T. Qg 10 V 50 kΩ Q Q 12 V 0.2 μF gs gd 0.3 μF + V V D.U.T. DS - G VGS Charge 3 mA
Fig. 18 - Basic Gate Charge Waveform
I I G D Current sampling resistors
Fig. 19 - Gate Charge Test Circuit Peak Diode Recovery dv/dt Test Circuit
+ Circuit layout considerations D.U.T. • Low stray inductance 3 • Ground plane • Low leakage inductance current transformer - + 2 - 4 + - 1 Rg • dv/dt controlled by R + g • Driver same type as D.U.T. V - DD • ISD controlled by duty factor “D” • D.U.T. - device under test 1 Driver gate drive P.W. Period D = P.W. Period VGS = 10 V a D.U.T. ISD waveform 2 Reverse recovery Body diode forward current current di/dt 3 D.U.T. V waveform DS Diode recovery dv/dt VDD Re-applied voltage Body diode forward drop Inductor current 4 Ripple ≤ 5 % ISD
Note
a. V = 5 V for logic level devices GS
Fig. 20 - For N-Channel
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package / tape drawings, part marking, and reliability data, see www.vishay.com/ppg?92290. S20-0109-Rev. B, 02-Mar-2020
6
Document Number: 92290 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000