Datasheet SLG46824 (Dialog Semiconductor) - 6

HerstellerDialog Semiconductor
BeschreibungGreenPAK Programmable Mixed-signal Matrix with In System Programmability
Seiten / Seite171 / 6 — SLG46824. GreenPAK Programmable Mixed-Signal Matrix with In System. …
Dateiformat / GrößePDF / 2.8 Mb
DokumentenspracheEnglisch

SLG46824. GreenPAK Programmable Mixed-Signal Matrix with In System. Programmability. Tables

SLG46824 GreenPAK Programmable Mixed-Signal Matrix with In System Programmability Tables

Modelllinie für dieses Datenblatt

Textversion des Dokuments

SLG46824
GreenPAK Programmable Mixed-Signal Matrix with In System
Programmability
Tables
Table 1: Functional Pin Description .
Table 2: Pin Type Definitions Table 3: Absolute Maximum Ratings Table 4: Electrostatic Discharge Ratings Table 5: Recommended Operating Conditions .
Table 6: EС at T = -40 °C to +85 °C, VDD = 2.3 V to 5.5 V Unless Otherwise Noted .
Table 7: EC of the I2C Pins at T = -40 °C to +85 °C, VDD = 2.3 V to 5.5 V Unless Otherwise Noted .
Table 8: I2C Pins Timing Characteristics at T = -40 °C to +85 °C, VDD = 2.3 V to 5.5 V Unless Otherwise Noted.
Table 9: Typical Current Estimated for Each Macrocell at T = -40 °C to +85 °C Table 10: Typical Delay Estimated for Each Macrocell at T = 25 °C Table 11: Programmable Delay Expected Delays and Widths (Typical) at T = 25 °C .
Table 12: Typical Filter Rejection Pulse Width at T = 25 °C Table 13: Typical Counter/Delay Offset Measurements at T = 25 °C Table 14: Oscillators Frequency Limits, VDD = 2.3 V to 5.5 V Table 15: Oscillators Power-On Delay at T = 25 °C, OSC Power Mode: "Auto Power-On" .
Table 16: ACMP Specifications at T = -40 °C to +85 °C, VDD = 2.3 V to 5.5 V Unless Otherwise Noted .
Table 17: Matrix Input Table .
Table 18: Matrix Output Table Table 19: Connection Matrix Virtual Inputs .
Table 20: 2-bit LUT0 Truth Table Table 21: 2-bit LUT1 Truth Table Table 22: 2-bit LUT2 Truth Table Table 23: 2-bit LUT Standard Digital Functions .
Table 24: 2-bit LUT1 Truth Table Table 25: 2-bit LUT Standard Digital Functions .
Table 26: 3-bit LUT0 Truth Table Table 27: 3-bit LUT1 Truth Table Table 28: 3-bit LUT2 Truth Table Table 29: 3-bit LUT3 Truth Table Table 30: 3-bit LUT4 Truth Table Table 31: 3-bit LUT5 Truth Table Table 32: 3-bit LUT Standard Digital Functions .
Table 33: 3-bit LUT6 Truth Table Table 34: 3-bit LUT7 Truth Table Table 35: 3-bit LUT8 Truth Table Table 36: 3-bit LUT9 Truth Table Table 37: 3-bit LUT10 Truth Table .
Table 38: 3-bit LUT11 Truth Table .
Table 39: 3-bit LUT12 Truth Table .
Table 40: 3-bit LUT13 Truth Table .
Table 41: 4-bit LUT0 Truth Table Table 42: 4-bit LUT Standard Digital Functions .
Table 43: Vref Selection Table .
Table 44: Oscillator Operation Mode Configuration Settings Table 45: Oscillator Output Duty Cycle .
Table 46: RPR Format .
Table 47: RPR Bit Function Description .
Table 48: NPR Format .
Table 49: NPR Bit Function Description .
Table 50: Read/Write Register Protection Options .
Table 51: Erase Register Bit format .
Table 52: Erase Register Bit Function Description .
Table 53: Register Map . Datasheet
CFR0011-120-00 Revision 3.10
6 of 171 . . . . . .9
. 12
. 13
. 13
. 13
. 14
. 19
. 20
. 21
. 21
. 24
. 24
. 24
. 25
. 25
. 25
. 37
. 38
. 42
. 45
. 45
. 45
. 45
. 48
. 48
. 52
. 52
. 52
. 52
. 52
. 52
. 53
. 58
. 68
. 68
. 68
. 68
. 68
. 68
. 68
. 80
. 80
. 88
. 92
101
110
110
111
111
111
117
117
118 10-Mar-2020
© 2020 Dialog Semiconductor