Datasheet SLG47004 (Dialog Semiconductor) - 6
| Hersteller | Dialog Semiconductor |
| Beschreibung | GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features |
| Seiten / Seite | 243 / 6 — SLG47004. Preliminary. Datasheet. Revision 2.1. 13-Nov-2020 |
| Dateiformat / Größe | PDF / 5.6 Mb |
| Dokumentensprache | Englisch |
SLG47004. Preliminary. Datasheet. Revision 2.1. 13-Nov-2020
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SLG47004
GreenPAK Programmable Mixed-Signal Matrix
Preliminary
with In-System Programmability and Advanced Analog Features Figure 56: Wake and Sleep Timing Diagram, Short Wake Mode, Counter Set is Used ..95 Figure 57: ACMP0L Block Diagram ...98 Figure 58: ACMP1L Block Diagram ...99 Figure 59: Chopper ACMP Block Diagram...100 Figure 60: ACMPx Power-On Delay vs. VDD..101 Figure 61: Programmable Operational Amplifier OA0, OA1 Internal Circuit ..102 Figure 62: Internal Operational Amplifier Circuit ..103 Figure 63: Example of Input Offset Voltage Compensation ...104 Figure 64: Instrumentation Amplifier Structure...105 Figure 65: Instrumentation Operational Amplifier Configuration for Users Trim...106 Figure 66: Typical Implementation of Voltage Regulator (A) and Current Sources (B, C)...107 Figure 67: Constant Current Sink...108 Figure 68: OpAmp0, 1 Input Offset Voltage vs. Input CM Voltage at T = 25 °C, VDDA = 2.4 V ..108 Figure 69: OpAmp0, 1 Input Offset Voltage vs. Input CM Voltage at T = 25 °C, VDDA = 5.5 V ..109 Figure 70: Internal OpAmp Input Offset Voltage vs. Input CM Voltage at T = 25 °C, VDDA = 2.4 V ...109 Figure 71: Internal OpAmp Input Offset Voltage vs. Input CM Voltage at T = 25 °C, VDDA = 5.5 V ...110 Figure 72: Open Loop Gain and Phase vs. Frequency VDD = 3.3 V for BW = 128 kHz.. 110 Figure 73: Open Loop Gain and Phase vs. Frequency VDD = 3.3 V for BW = 512 kHz.. 111 Figure 74: Open Loop Gain and Phase vs. Frequency VDD = 3.3 V for BW = 2 MHz .. 111 Figure 75: Open Loop Gain and Phase vs. Frequency VDD = 3.3 V for BW = 8 MHz .. 112 Figure 76: PSRR vs. Frequency VDD = 2.4 V to 5.5 V ..112 Figure 77: Slew Rate vs. Ambient Temperature G = 1 V/V; RL = 50 kΩ for BW = 128 kHz .. 113 Figure 78: Slew Rate vs. Ambient Temperature G = 1 V/V; RL = 50 kΩ for BW = 512 kHz .. 113 Figure 79: Slew Rate vs. Ambient Temperature G = 1 V/V; RL = 50 kΩ for BW = 2 MHz ... 114 Figure 80: Slew Rate vs. Ambient Temperature G = 1 V/V; RL = 50 kΩ for BW = 8 MHz.. 114 Figure 81: Output Voltage Low (VOUT - GND) vs. Temperature at BW = 128 kHz, RLOAD = 600 Ω ..115 Figure 82: Output Voltage Low (VOUT - GND) vs. Temperature at BW = 128 kHz, RLOAD = 50 kΩ ..115 Figure 83: Output Voltage High (VDDA- VOUT) vs. Temperature at BW = 128 kHz, RLOAD = 600 Ω..116 Figure 84: Output Voltage High (VDDA- VOUT) vs. Temperature at BW = 128 kHz, RLOAD = 50 kΩ..116 Figure 85: Output Voltage Low (VOUT - GND) vs. Temperature at BW = 512 kHz, RLOAD = 50 kΩ ..117 Figure 86: Output Voltage Low (VOUT - GND) vs. Temperature at BW = 512 kHz, RLOAD = 50 kΩ ..117 Figure 87: Output Voltage High (VDDA- VOUT) vs. Temperature at BW = 512 kHz, RLOAD = 600 Ω..118 Figure 88: Output Voltage High (VDDA- VOUT) vs. Temperature at BW = 512kHz, RLOAD = 50 kΩ...118 Figure 89: Output Voltage Low (VOUT - GND) vs. Temperature at BW = 2 MHz, RLOAD = 600 Ω...119 Figure 90: Output Voltage Low (VOUT - GND) vs. Temperature at BW = 2 MHz, RLOAD = 50 kΩ...119 Figure 91: Output Voltage High (VDDA- VOUT) vs. Temperature at BW = 2 MHz, RLOAD = 600 Ω ..120 Figure 92: Output Voltage High (VDDA- VOUT) vs. Temperature at BW = 2 MHz, RLOAD = 50 kΩ...120 Figure 93: Output Voltage Low (VOUT - GND) vs. Temperature at BW = 8MHz, RLOAD = 600 Ω..121 Figure 94: Output Voltage Low (VOUT - GND) vs. Temperature at BW = 8 MHz, RLOAD = 50 kΩ...121 Figure 95: Output Voltage High (VDDA- VOUT) vs. Temperature at BW = 8 MHz, RLOAD = 600 Ω ..122 Figure 96: Output Voltage High (VDDA- VOUT) vs. Temperature at BW = 8 MHz, RLOAD = 50 kΩ...122 Figure 97: Overload Recovery Time vs. Power Supply Voltage RL= 50 kΩ; G = 1 V/V, Rising...123 Figure 98: Overload Recovery Time vs. Power Supply Voltage RL= 50 kΩ; G = 1 V/V, Fal ing ..123 Figure 99: Analog Switch 0 Control Circuit...124 Figure 100: Analog Switch 1 Control Circuit...125 Figure 101: Structure of Half Bridge...126 Figure 102: Programmable Trim Blocks and Digital Rheostat’s Internal Circuit...128 Figure 103: Rheostats in Potentiometer Mode..129 Figure 104: Rheostat Tolerance Registers..130 Figure 105: Flowchart of "Program" and "Reload" Signals ..131 Figure 106: Example of Latching and Processing "Program" and "Reload" Signals..132 Figure 107: Example of Auto-Trim Process for a Single Rheostat...134 Figure 108: Example of Auto-Trim Process with External Clock Signal...135 Figure 109: Example of Auto-Trim Process for Two Rheostats ...136 Figure 110: Example of Auto-Trim Process via I2C..137 Figure 111: Example of Hardware Configuration ...138 Figure 112: Example of User Specific Trimming Process under I2C Master Control ...139
Datasheet Revision 2.1 13-Nov-2020
CFR0011-120-00 6 of 243 © 2020 Dialog Semiconductor Document Outline General Description Key Features Applications 1 Block Diagram 2 Pinout 2.1 Pin Configuration - STQFN-24L 3 Characteristics 3.1 Absolute Maximum Ratings 3.2 Electrostatic Discharge Ratings 3.3 Recommended Operating Conditions 3.4 Electrical Characteristics 3.5 Timing Characteristics 3.6 Oscillator Characteristics 3.6.1 OSC Power-On Delay 3.7 ACMP Characteristics 3.8 Internal Vref Characteristics 3.9 Output Buffers Characteristics 3.10 Analog Temperature Sensor Characteristics 3.11 Programmable Operational Amplifier Characteristics 3.12 100K Digital Rheostat Characteristics 3.13 Analog Switches Characteristics 4 User Programmability 5 IO Pins 5.1 GPIO Pins 5.2 GPI Pins 5.3 Pull-Up/Down Resistors 5.4 Fast Pull-Up/Down during Power-Up 5.5 I2C Mode IO Structure 5.5.1 I2C Mode Structure (for SCL and SDA) 5.6 Matrix OE IO Structure 5.7 GPI Structure 5.7.1 GPI Structure (for I0) 5.8 IO Pins Typical Performance 6 Connection Matrix 6.1 Matrix Input Table 6.2 Matrix Output Table 6.3 Connection Matrix Virtual Inputs 6.4 Connection Matrix Virtual Outputs 7 Combination Function Macrocells 7.1 2-Bit LUT or D Flip-Flop Macrocells 7.1.1 2-Bit LUT or D Flip-Flop Macrocell Used as 2-Bit LUT 7.1.2 Initial Polarity Operations 7.2 2-bit LUT or Programmable Pattern Generator 7.2.1 2-Bit LUT or PGen Macrocell Used as 2-Bit LUT 7.3 3-Bit LUT or D Flip-Flop with Set/Reset Macrocells 7.3.1 3-Bit LUT or D Flip-Flop Macrocells Used as 3-Bit LUTs 7.3.2 Initial Polarity Operations 7.4 4-Bit LUT or D Flip-Flop with Set/Reset Macrocell 7.4.1 4-Bit LUT Macrocell Used as 4-Bit LUT 7.5 3-Bit LUT or Pipe Delay/Ripple Counter Macrocell 7.5.1 3-Bit LUT or Pipe Delay Macrocells Used as 3-Bit LUT 8 Multi-Function Macrocells 8.1 3-Bit LUT or DFF/Latch with 8-Bit Counter/Delay Macrocells 8.1.1 3-Bit LUT or 8-Bit CNT/DLY Block Diagrams 8.1.2 3-Bit LUT or CNT/DLYs Used as 3-Bit LUTs 8.2 4-Bit LUT or DFF/Latch with 16-Bit Counter/Delay Macrocell 8.2.1 4-Bit LUT or DFF/LATCH with 16-Bit CNT/DLY Block Diagram 8.2.2 4-Bit LUT or 16-Bit Counter/Delay Macrocells Used as 4-Bit LUTs 8.3 CNT/DLY/FSM Timing Diagrams 8.3.1 Delay Mode CNT/DLY0 to CNT/DLY6 8.3.2 Count Mode (Count Data: 3), Counter Reset (Rising Edge Detect) CNT/DLY0 to CNT/DLY6 8.3.3 One-Shot Mode CNT/DLY0 to CNT/DLY6 8.3.4 Frequency Detection Mode CNT/DLY0 to CNT/DLY6 8.3.5 Edge Detection Mode CNT/DLY1 to CNT/DLY6 8.3.6 Delayed Edge Detection Mode CNT/DLY0 to CNT/DLY6 8.3.7 CNT/FSM Mode CNT/DLY0 8.3.8 Difference in Counter Value for Counter, Delay, One-Shot, and Frequency Detect Modes 8.4 Wake and Sleep Controller 9 Analog Comparators 9.1 Analog Comparators Overview 9.1.1 ACMP0L Block Diagram 9.1.2 ACMP1L Block Diagram 9.2 Chopper Analog Comparator 9.3 ACMP Sampling Mode 9.4 ACMP Typical Performance 10 Programmable Operational Amplifiers 10.1 General Description 10.2 Modes of Operation 10.2.1 Operational Amplifier Mode 10.2.2 Instrumentation Amplifier Mode 10.2.3 Analog Comparator Mode 10.2.4 Voltage Regulator Mode 10.2.5 Current Sink Mode 10.3 Op Amp Typical Performance 11 Analog Switch Macrocell 11.1 Analog Switch General Description 11.2 Half Bridge Mode 12 Digital Rheostats and Programmable Trim Block 12.1 Potentiometer Mode 12.2 Calculating Actual Resistance 12.3 Digital Rheostat Value Self-programming into the NVM 12.4 Trimming process Using Programmable Trim Block 12.4.1 Trimming Process with Auto-Trim Option Enabled 12.4.2 I2C Controlled Trimming Process with Auto-Trim Option Enabled 12.4.3 Changing Rheostat Value Directly via I2C 12.5 Using Chopper ACMP 13 Programmable Delay/Edge Detector 13.1 Programmable Delay Timing Diagram - Edge Detector Output 14 Additional Logic Function. Deglitch Filter 15 Voltage Reference 15.1 Voltage Reference Overview 15.2 Vref Selection Table 15.3 Vref Block Diagram 16 Clocking 16.1 OSC General Description 16.2 Oscillator0 (2.048 kHz) 16.3 Oscillator1 (2.048 MHz) 16.4 Oscillator2 (25 MHz) 16.5 CNT/DLY Clock Scheme 16.6 External Clocking 16.6.1 IO1 Source for Oscillator0 (2.048 kHz) 16.6.2 IO3 Source for Oscillator1 (2.048 MHz) 16.6.3 IO2 Source for Oscillator2 (25 MHz) 16.7 Oscillators Power-On Delay 16.8 Oscillators Accuracy 17 Power-On Reset 17.1 General Operation 17.2 POR Sequence 17.3 Macrocells Output States During POR Sequence 17.3.1 Initialization 17.3.2 Power-Down 18 I2C Serial Communications Macrocell 18.1 I2C Serial Communications Macrocell Overview 18.2 I2C Serial Communications Device Addressing 18.3 I2C Serial General Timing 18.4 I2C Serial Communications Commands 18.4.1 Byte Write Command 18.4.2 Sequential Write Command 18.4.3 Current Address Read Command 18.4.4 Random Read Command 18.4.5 Sequential Read Command 18.4.6 I2C Serial Reset Command 18.5 Chip Configuration Data Protection 18.6 I2C Serial Command Register Map 18.7 I2C Additional Options 18.7.1 Reading Counter Data via I2C 18.7.2 I2C Byte Write Bit Masking 19 Non-Volatile Memory 19.1 Serial NVM Write Operations 19.2 Serial NVM Read Operations 19.3 Serial NVM Erase Operations 19.4 Acknowledge Polling 19.5 Low power standby mode 19.6 Emulated EEPROM Write Protection 20 Analog Temperature Sensor 21 Register Definitions 21.1 Register Map 22 Package Top Marking System Definition 22.1 STQFN-24L 3 mm x 3 mm x 0.55 mm, 0.4P FCD Package 23 Package Information 23.1 Package outlines FOR STQFN 24L 3 mm x 3 mm x 0.55 mm 0.4P Green Package 23.2 STQFN Handling 23.3 Soldering Information 24 Ordering Information 24.1 Tape and Reel Specifications 25 Layout Guidelines 25.1 STQFN 24L 3 mm x 3 mm x 0.55 mm 0.4P Green Package Glossary Revision History
SLG47004
GreenPAK Programmable Mixed-Signal Matrix
Preliminary
with In-System Programmability and Advanced Analog Features Figure 56: Wake and Sleep Timing Diagram, Short Wake Mode, Counter Set is Used ..95 Figure 57: ACMP0L Block Diagram ...98 Figure 58: ACMP1L Block Diagram ...99 Figure 59: Chopper ACMP Block Diagram...100 Figure 60: ACMPx Power-On Delay vs. VDD..101 Figure 61: Programmable Operational Amplifier OA0, OA1 Internal Circuit ..102 Figure 62: Internal Operational Amplifier Circuit ..103 Figure 63: Example of Input Offset Voltage Compensation ...104 Figure 64: Instrumentation Amplifier Structure...105 Figure 65: Instrumentation Operational Amplifier Configuration for Users Trim...106 Figure 66: Typical Implementation of Voltage Regulator (A) and Current Sources (B, C)...107 Figure 67: Constant Current Sink...108 Figure 68: OpAmp0, 1 Input Offset Voltage vs. Input CM Voltage at T = 25 °C, VDDA = 2.4 V ..108 Figure 69: OpAmp0, 1 Input Offset Voltage vs. Input CM Voltage at T = 25 °C, VDDA = 5.5 V ..109 Figure 70: Internal OpAmp Input Offset Voltage vs. Input CM Voltage at T = 25 °C, VDDA = 2.4 V ...109 Figure 71: Internal OpAmp Input Offset Voltage vs. Input CM Voltage at T = 25 °C, VDDA = 5.5 V ...110 Figure 72: Open Loop Gain and Phase vs. Frequency VDD = 3.3 V for BW = 128 kHz.. 110 Figure 73: Open Loop Gain and Phase vs. Frequency VDD = 3.3 V for BW = 512 kHz.. 111 Figure 74: Open Loop Gain and Phase vs. Frequency VDD = 3.3 V for BW = 2 MHz .. 111 Figure 75: Open Loop Gain and Phase vs. Frequency VDD = 3.3 V for BW = 8 MHz .. 112 Figure 76: PSRR vs. Frequency VDD = 2.4 V to 5.5 V ..112 Figure 77: Slew Rate vs. Ambient Temperature G = 1 V/V; RL = 50 kΩ for BW = 128 kHz .. 113 Figure 78: Slew Rate vs. Ambient Temperature G = 1 V/V; RL = 50 kΩ for BW = 512 kHz .. 113 Figure 79: Slew Rate vs. Ambient Temperature G = 1 V/V; RL = 50 kΩ for BW = 2 MHz ... 114 Figure 80: Slew Rate vs. Ambient Temperature G = 1 V/V; RL = 50 kΩ for BW = 8 MHz.. 114 Figure 81: Output Voltage Low (VOUT - GND) vs. Temperature at BW = 128 kHz, RLOAD = 600 Ω ..115 Figure 82: Output Voltage Low (VOUT - GND) vs. Temperature at BW = 128 kHz, RLOAD = 50 kΩ ..115 Figure 83: Output Voltage High (VDDA- VOUT) vs. Temperature at BW = 128 kHz, RLOAD = 600 Ω..116 Figure 84: Output Voltage High (VDDA- VOUT) vs. Temperature at BW = 128 kHz, RLOAD = 50 kΩ..116 Figure 85: Output Voltage Low (VOUT - GND) vs. Temperature at BW = 512 kHz, RLOAD = 50 kΩ ..117 Figure 86: Output Voltage Low (VOUT - GND) vs. Temperature at BW = 512 kHz, RLOAD = 50 kΩ ..117 Figure 87: Output Voltage High (VDDA- VOUT) vs. Temperature at BW = 512 kHz, RLOAD = 600 Ω..118 Figure 88: Output Voltage High (VDDA- VOUT) vs. Temperature at BW = 512kHz, RLOAD = 50 kΩ...118 Figure 89: Output Voltage Low (VOUT - GND) vs. Temperature at BW = 2 MHz, RLOAD = 600 Ω...119 Figure 90: Output Voltage Low (VOUT - GND) vs. Temperature at BW = 2 MHz, RLOAD = 50 kΩ...119 Figure 91: Output Voltage High (VDDA- VOUT) vs. Temperature at BW = 2 MHz, RLOAD = 600 Ω ..120 Figure 92: Output Voltage High (VDDA- VOUT) vs. Temperature at BW = 2 MHz, RLOAD = 50 kΩ...120 Figure 93: Output Voltage Low (VOUT - GND) vs. Temperature at BW = 8MHz, RLOAD = 600 Ω..121 Figure 94: Output Voltage Low (VOUT - GND) vs. Temperature at BW = 8 MHz, RLOAD = 50 kΩ...121 Figure 95: Output Voltage High (VDDA- VOUT) vs. Temperature at BW = 8 MHz, RLOAD = 600 Ω ..122 Figure 96: Output Voltage High (VDDA- VOUT) vs. Temperature at BW = 8 MHz, RLOAD = 50 kΩ...122 Figure 97: Overload Recovery Time vs. Power Supply Voltage RL= 50 kΩ; G = 1 V/V, Rising...123 Figure 98: Overload Recovery Time vs. Power Supply Voltage RL= 50 kΩ; G = 1 V/V, Fal ing ..123 Figure 99: Analog Switch 0 Control Circuit...124 Figure 100: Analog Switch 1 Control Circuit...125 Figure 101: Structure of Half Bridge...126 Figure 102: Programmable Trim Blocks and Digital Rheostat’s Internal Circuit...128 Figure 103: Rheostats in Potentiometer Mode..129 Figure 104: Rheostat Tolerance Registers..130 Figure 105: Flowchart of "Program" and "Reload" Signals ..131 Figure 106: Example of Latching and Processing "Program" and "Reload" Signals..132 Figure 107: Example of Auto-Trim Process for a Single Rheostat...134 Figure 108: Example of Auto-Trim Process with External Clock Signal...135 Figure 109: Example of Auto-Trim Process for Two Rheostats ...136 Figure 110: Example of Auto-Trim Process via I2C..137 Figure 111: Example of Hardware Configuration ...138 Figure 112: Example of User Specific Trimming Process under I2C Master Control ...139
Datasheet Revision 2.1 13-Nov-2020
CFR0011-120-00 6 of 243 © 2020 Dialog Semiconductor Document Outline General Description Key Features Applications 1 Block Diagram 2 Pinout 2.1 Pin Configuration - STQFN-24L 3 Characteristics 3.1 Absolute Maximum Ratings 3.2 Electrostatic Discharge Ratings 3.3 Recommended Operating Conditions 3.4 Electrical Characteristics 3.5 Timing Characteristics 3.6 Oscillator Characteristics 3.6.1 OSC Power-On Delay 3.7 ACMP Characteristics 3.8 Internal Vref Characteristics 3.9 Output Buffers Characteristics 3.10 Analog Temperature Sensor Characteristics 3.11 Programmable Operational Amplifier Characteristics 3.12 100K Digital Rheostat Characteristics 3.13 Analog Switches Characteristics 4 User Programmability 5 IO Pins 5.1 GPIO Pins 5.2 GPI Pins 5.3 Pull-Up/Down Resistors 5.4 Fast Pull-Up/Down during Power-Up 5.5 I2C Mode IO Structure 5.5.1 I2C Mode Structure (for SCL and SDA) 5.6 Matrix OE IO Structure 5.7 GPI Structure 5.7.1 GPI Structure (for I0) 5.8 IO Pins Typical Performance 6 Connection Matrix 6.1 Matrix Input Table 6.2 Matrix Output Table 6.3 Connection Matrix Virtual Inputs 6.4 Connection Matrix Virtual Outputs 7 Combination Function Macrocells 7.1 2-Bit LUT or D Flip-Flop Macrocells 7.1.1 2-Bit LUT or D Flip-Flop Macrocell Used as 2-Bit LUT 7.1.2 Initial Polarity Operations 7.2 2-bit LUT or Programmable Pattern Generator 7.2.1 2-Bit LUT or PGen Macrocell Used as 2-Bit LUT 7.3 3-Bit LUT or D Flip-Flop with Set/Reset Macrocells 7.3.1 3-Bit LUT or D Flip-Flop Macrocells Used as 3-Bit LUTs 7.3.2 Initial Polarity Operations 7.4 4-Bit LUT or D Flip-Flop with Set/Reset Macrocell 7.4.1 4-Bit LUT Macrocell Used as 4-Bit LUT 7.5 3-Bit LUT or Pipe Delay/Ripple Counter Macrocell 7.5.1 3-Bit LUT or Pipe Delay Macrocells Used as 3-Bit LUT 8 Multi-Function Macrocells 8.1 3-Bit LUT or DFF/Latch with 8-Bit Counter/Delay Macrocells 8.1.1 3-Bit LUT or 8-Bit CNT/DLY Block Diagrams 8.1.2 3-Bit LUT or CNT/DLYs Used as 3-Bit LUTs 8.2 4-Bit LUT or DFF/Latch with 16-Bit Counter/Delay Macrocell 8.2.1 4-Bit LUT or DFF/LATCH with 16-Bit CNT/DLY Block Diagram 8.2.2 4-Bit LUT or 16-Bit Counter/Delay Macrocells Used as 4-Bit LUTs 8.3 CNT/DLY/FSM Timing Diagrams 8.3.1 Delay Mode CNT/DLY0 to CNT/DLY6 8.3.2 Count Mode (Count Data: 3), Counter Reset (Rising Edge Detect) CNT/DLY0 to CNT/DLY6 8.3.3 One-Shot Mode CNT/DLY0 to CNT/DLY6 8.3.4 Frequency Detection Mode CNT/DLY0 to CNT/DLY6 8.3.5 Edge Detection Mode CNT/DLY1 to CNT/DLY6 8.3.6 Delayed Edge Detection Mode CNT/DLY0 to CNT/DLY6 8.3.7 CNT/FSM Mode CNT/DLY0 8.3.8 Difference in Counter Value for Counter, Delay, One-Shot, and Frequency Detect Modes 8.4 Wake and Sleep Controller 9 Analog Comparators 9.1 Analog Comparators Overview 9.1.1 ACMP0L Block Diagram 9.1.2 ACMP1L Block Diagram 9.2 Chopper Analog Comparator 9.3 ACMP Sampling Mode 9.4 ACMP Typical Performance 10 Programmable Operational Amplifiers 10.1 General Description 10.2 Modes of Operation 10.2.1 Operational Amplifier Mode 10.2.2 Instrumentation Amplifier Mode 10.2.3 Analog Comparator Mode 10.2.4 Voltage Regulator Mode 10.2.5 Current Sink Mode 10.3 Op Amp Typical Performance 11 Analog Switch Macrocell 11.1 Analog Switch General Description 11.2 Half Bridge Mode 12 Digital Rheostats and Programmable Trim Block 12.1 Potentiometer Mode 12.2 Calculating Actual Resistance 12.3 Digital Rheostat Value Self-programming into the NVM 12.4 Trimming process Using Programmable Trim Block 12.4.1 Trimming Process with Auto-Trim Option Enabled 12.4.2 I2C Controlled Trimming Process with Auto-Trim Option Enabled 12.4.3 Changing Rheostat Value Directly via I2C 12.5 Using Chopper ACMP 13 Programmable Delay/Edge Detector 13.1 Programmable Delay Timing Diagram - Edge Detector Output 14 Additional Logic Function. Deglitch Filter 15 Voltage Reference 15.1 Voltage Reference Overview 15.2 Vref Selection Table 15.3 Vref Block Diagram 16 Clocking 16.1 OSC General Description 16.2 Oscillator0 (2.048 kHz) 16.3 Oscillator1 (2.048 MHz) 16.4 Oscillator2 (25 MHz) 16.5 CNT/DLY Clock Scheme 16.6 External Clocking 16.6.1 IO1 Source for Oscillator0 (2.048 kHz) 16.6.2 IO3 Source for Oscillator1 (2.048 MHz) 16.6.3 IO2 Source for Oscillator2 (25 MHz) 16.7 Oscillators Power-On Delay 16.8 Oscillators Accuracy 17 Power-On Reset 17.1 General Operation 17.2 POR Sequence 17.3 Macrocells Output States During POR Sequence 17.3.1 Initialization 17.3.2 Power-Down 18 I2C Serial Communications Macrocell 18.1 I2C Serial Communications Macrocell Overview 18.2 I2C Serial Communications Device Addressing 18.3 I2C Serial General Timing 18.4 I2C Serial Communications Commands 18.4.1 Byte Write Command 18.4.2 Sequential Write Command 18.4.3 Current Address Read Command 18.4.4 Random Read Command 18.4.5 Sequential Read Command 18.4.6 I2C Serial Reset Command 18.5 Chip Configuration Data Protection 18.6 I2C Serial Command Register Map 18.7 I2C Additional Options 18.7.1 Reading Counter Data via I2C 18.7.2 I2C Byte Write Bit Masking 19 Non-Volatile Memory 19.1 Serial NVM Write Operations 19.2 Serial NVM Read Operations 19.3 Serial NVM Erase Operations 19.4 Acknowledge Polling 19.5 Low power standby mode 19.6 Emulated EEPROM Write Protection 20 Analog Temperature Sensor 21 Register Definitions 21.1 Register Map 22 Package Top Marking System Definition 22.1 STQFN-24L 3 mm x 3 mm x 0.55 mm, 0.4P FCD Package 23 Package Information 23.1 Package outlines FOR STQFN 24L 3 mm x 3 mm x 0.55 mm 0.4P Green Package 23.2 STQFN Handling 23.3 Soldering Information 24 Ordering Information 24.1 Tape and Reel Specifications 25 Layout Guidelines 25.1 STQFN 24L 3 mm x 3 mm x 0.55 mm 0.4P Green Package Glossary Revision History