Datasheet SLG47004 (Dialog Semiconductor) - 3
| Hersteller | Dialog Semiconductor |
| Beschreibung | GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features |
| Seiten / Seite | 243 / 3 — SLG47004. Preliminary. 11 Analog Switch Macrocell ... 123. 12 Digital … |
| Dateiformat / Größe | PDF / 5.6 Mb |
| Dokumentensprache | Englisch |
SLG47004. Preliminary. 11 Analog Switch Macrocell ... 123. 12 Digital Rheostats and Programmable Trim Block ... 126
Modelllinie für dieses Datenblatt
Textversion des Dokuments
link to page 123 link to page 123 link to page 125 link to page 126 link to page 128 link to page 128 link to page 129 link to page 132 link to page 138 link to page 139 link to page 139 link to page 140 link to page 141 link to page 141 link to page 141 link to page 143 link to page 147 link to page 147 link to page 148 link to page 149 link to page 150 link to page 150 link to page 151 link to page 152 link to page 152 link to page 153 link to page 153 link to page 154 link to page 154 link to page 157 link to page 157 link to page 157 link to page 158 link to page 158 link to page 161 link to page 162 link to page 165 link to page 167 link to page 167 link to page 169 link to page 169 link to page 170 link to page 170 link to page 170 link to page 172 link to page 175 link to page 175 link to page 235 link to page 235 link to page 236 link to page 236 link to page 236 link to page 236 link to page 237 link to page 237 link to page 238 link to page 238
SLG47004
GreenPAK Programmable Mixed-Signal Matrix
Preliminary
with In-System Programmability and Advanced Analog Features
11 Analog Switch Macrocell ... 123
11.1 Analog Switch General Description ..123 11.2 Half Bridge Mode ...125
12 Digital Rheostats and Programmable Trim Block ... 126
12.1 Potentiometer Mode ...128 12.2 Calculating Actual Resistance ..128 12.3 Digital Rheostat Value Self-programming into the NVM ..129 12.4 Trimming process Using Programmable Trim Block ..132 12.5 Using Chopper ACMP ..138
13 Programmable Delay/Edge Detector .. 139
13.1 Programmable Delay Timing Diagram - Edge Detector Output ...139
14 Additional Logic Function. Deglitch Filter ... 140 15 Voltage Reference .. 141
15.1 Voltage Reference Overview ...141 15.2 Vref Selection Table ..141 15.3 Vref Block Diagram ..143
16 Clocking .. 147
16.1 OSC General Description ...147 16.2 Oscillator0 (2.048 kHz) ...148 16.3 Oscillator1 (2.048 MHz) ...149 16.4 Oscillator2 (25 MHz) ..150 16.5 CNT/DLY Clock Scheme ..150 16.6 External Clocking ...151 16.7 Oscillators Power-On Delay ...152 16.8 Oscillators Accuracy ...152
17 Power-On Reset .. 153
17.1 General Operation ..153 17.2 POR Sequence ..154 17.3 Macrocel s Output States During POR Sequence ...154
18 I
2
C Serial Communications Macrocell .. 157
18.1 I2C Serial Communications Macrocel Overview ..157 18.2 I2C Serial Communications Device Addressing ...157 18.3 I2C Serial General Timing ..158 18.4 I2C Serial Communications Commands ...158 18.5 Chip Configuration Data Protection ..161 18.6 I2C Serial Command Register Map ..162 18.7 I2C Additional Options ..165
19 Non-Volatile Memory .. 167
19.1 Serial NVM Write Operations ...167 19.2 Serial NVM Read Operations ...169 19.3 Serial NVM Erase Operations ..169 19.4 Acknowledge Pol ing ..170 19.5 Low power standby mode ..170 19.6 Emulated EEPROM Write Protection ...170
20 Analog Temperature Sensor ... 172 21 Register Definitions ... 175
21.1 Register Map ..175
22 Package Top Marking System Definition ... 235
22.1 STQFN-24L 3 mm x 3 mm x 0.55 mm, 0.4P FCD Package ..235
23 Package Information .. 236
23.1 Package outlines FOR STQFN 24L 3 mm x 3 mm x 0.55 mm 0.4P Green Package ..236 23.2 STQFN Handling ..236 23.3 Soldering Information ...236
24 Ordering Information ... 237
24.1 Tape and Reel Specifications ..237
25 Layout Guidelines .. 238
25.1 STQFN 24L 3 mm x 3 mm x 0.55 mm 0.4P Green Package ...238
Datasheet Revision 2.1 13-Nov-2020
CFR0011-120-00 3 of 243 © 2020 Dialog Semiconductor Document Outline General Description Key Features Applications 1 Block Diagram 2 Pinout 2.1 Pin Configuration - STQFN-24L 3 Characteristics 3.1 Absolute Maximum Ratings 3.2 Electrostatic Discharge Ratings 3.3 Recommended Operating Conditions 3.4 Electrical Characteristics 3.5 Timing Characteristics 3.6 Oscillator Characteristics 3.6.1 OSC Power-On Delay 3.7 ACMP Characteristics 3.8 Internal Vref Characteristics 3.9 Output Buffers Characteristics 3.10 Analog Temperature Sensor Characteristics 3.11 Programmable Operational Amplifier Characteristics 3.12 100K Digital Rheostat Characteristics 3.13 Analog Switches Characteristics 4 User Programmability 5 IO Pins 5.1 GPIO Pins 5.2 GPI Pins 5.3 Pull-Up/Down Resistors 5.4 Fast Pull-Up/Down during Power-Up 5.5 I2C Mode IO Structure 5.5.1 I2C Mode Structure (for SCL and SDA) 5.6 Matrix OE IO Structure 5.7 GPI Structure 5.7.1 GPI Structure (for I0) 5.8 IO Pins Typical Performance 6 Connection Matrix 6.1 Matrix Input Table 6.2 Matrix Output Table 6.3 Connection Matrix Virtual Inputs 6.4 Connection Matrix Virtual Outputs 7 Combination Function Macrocells 7.1 2-Bit LUT or D Flip-Flop Macrocells 7.1.1 2-Bit LUT or D Flip-Flop Macrocell Used as 2-Bit LUT 7.1.2 Initial Polarity Operations 7.2 2-bit LUT or Programmable Pattern Generator 7.2.1 2-Bit LUT or PGen Macrocell Used as 2-Bit LUT 7.3 3-Bit LUT or D Flip-Flop with Set/Reset Macrocells 7.3.1 3-Bit LUT or D Flip-Flop Macrocells Used as 3-Bit LUTs 7.3.2 Initial Polarity Operations 7.4 4-Bit LUT or D Flip-Flop with Set/Reset Macrocell 7.4.1 4-Bit LUT Macrocell Used as 4-Bit LUT 7.5 3-Bit LUT or Pipe Delay/Ripple Counter Macrocell 7.5.1 3-Bit LUT or Pipe Delay Macrocells Used as 3-Bit LUT 8 Multi-Function Macrocells 8.1 3-Bit LUT or DFF/Latch with 8-Bit Counter/Delay Macrocells 8.1.1 3-Bit LUT or 8-Bit CNT/DLY Block Diagrams 8.1.2 3-Bit LUT or CNT/DLYs Used as 3-Bit LUTs 8.2 4-Bit LUT or DFF/Latch with 16-Bit Counter/Delay Macrocell 8.2.1 4-Bit LUT or DFF/LATCH with 16-Bit CNT/DLY Block Diagram 8.2.2 4-Bit LUT or 16-Bit Counter/Delay Macrocells Used as 4-Bit LUTs 8.3 CNT/DLY/FSM Timing Diagrams 8.3.1 Delay Mode CNT/DLY0 to CNT/DLY6 8.3.2 Count Mode (Count Data: 3), Counter Reset (Rising Edge Detect) CNT/DLY0 to CNT/DLY6 8.3.3 One-Shot Mode CNT/DLY0 to CNT/DLY6 8.3.4 Frequency Detection Mode CNT/DLY0 to CNT/DLY6 8.3.5 Edge Detection Mode CNT/DLY1 to CNT/DLY6 8.3.6 Delayed Edge Detection Mode CNT/DLY0 to CNT/DLY6 8.3.7 CNT/FSM Mode CNT/DLY0 8.3.8 Difference in Counter Value for Counter, Delay, One-Shot, and Frequency Detect Modes 8.4 Wake and Sleep Controller 9 Analog Comparators 9.1 Analog Comparators Overview 9.1.1 ACMP0L Block Diagram 9.1.2 ACMP1L Block Diagram 9.2 Chopper Analog Comparator 9.3 ACMP Sampling Mode 9.4 ACMP Typical Performance 10 Programmable Operational Amplifiers 10.1 General Description 10.2 Modes of Operation 10.2.1 Operational Amplifier Mode 10.2.2 Instrumentation Amplifier Mode 10.2.3 Analog Comparator Mode 10.2.4 Voltage Regulator Mode 10.2.5 Current Sink Mode 10.3 Op Amp Typical Performance 11 Analog Switch Macrocell 11.1 Analog Switch General Description 11.2 Half Bridge Mode 12 Digital Rheostats and Programmable Trim Block 12.1 Potentiometer Mode 12.2 Calculating Actual Resistance 12.3 Digital Rheostat Value Self-programming into the NVM 12.4 Trimming process Using Programmable Trim Block 12.4.1 Trimming Process with Auto-Trim Option Enabled 12.4.2 I2C Controlled Trimming Process with Auto-Trim Option Enabled 12.4.3 Changing Rheostat Value Directly via I2C 12.5 Using Chopper ACMP 13 Programmable Delay/Edge Detector 13.1 Programmable Delay Timing Diagram - Edge Detector Output 14 Additional Logic Function. Deglitch Filter 15 Voltage Reference 15.1 Voltage Reference Overview 15.2 Vref Selection Table 15.3 Vref Block Diagram 16 Clocking 16.1 OSC General Description 16.2 Oscillator0 (2.048 kHz) 16.3 Oscillator1 (2.048 MHz) 16.4 Oscillator2 (25 MHz) 16.5 CNT/DLY Clock Scheme 16.6 External Clocking 16.6.1 IO1 Source for Oscillator0 (2.048 kHz) 16.6.2 IO3 Source for Oscillator1 (2.048 MHz) 16.6.3 IO2 Source for Oscillator2 (25 MHz) 16.7 Oscillators Power-On Delay 16.8 Oscillators Accuracy 17 Power-On Reset 17.1 General Operation 17.2 POR Sequence 17.3 Macrocells Output States During POR Sequence 17.3.1 Initialization 17.3.2 Power-Down 18 I2C Serial Communications Macrocell 18.1 I2C Serial Communications Macrocell Overview 18.2 I2C Serial Communications Device Addressing 18.3 I2C Serial General Timing 18.4 I2C Serial Communications Commands 18.4.1 Byte Write Command 18.4.2 Sequential Write Command 18.4.3 Current Address Read Command 18.4.4 Random Read Command 18.4.5 Sequential Read Command 18.4.6 I2C Serial Reset Command 18.5 Chip Configuration Data Protection 18.6 I2C Serial Command Register Map 18.7 I2C Additional Options 18.7.1 Reading Counter Data via I2C 18.7.2 I2C Byte Write Bit Masking 19 Non-Volatile Memory 19.1 Serial NVM Write Operations 19.2 Serial NVM Read Operations 19.3 Serial NVM Erase Operations 19.4 Acknowledge Polling 19.5 Low power standby mode 19.6 Emulated EEPROM Write Protection 20 Analog Temperature Sensor 21 Register Definitions 21.1 Register Map 22 Package Top Marking System Definition 22.1 STQFN-24L 3 mm x 3 mm x 0.55 mm, 0.4P FCD Package 23 Package Information 23.1 Package outlines FOR STQFN 24L 3 mm x 3 mm x 0.55 mm 0.4P Green Package 23.2 STQFN Handling 23.3 Soldering Information 24 Ordering Information 24.1 Tape and Reel Specifications 25 Layout Guidelines 25.1 STQFN 24L 3 mm x 3 mm x 0.55 mm 0.4P Green Package Glossary Revision History
SLG47004
GreenPAK Programmable Mixed-Signal Matrix
Preliminary
with In-System Programmability and Advanced Analog Features
11 Analog Switch Macrocell ... 123
11.1 Analog Switch General Description ..123 11.2 Half Bridge Mode ...125
12 Digital Rheostats and Programmable Trim Block ... 126
12.1 Potentiometer Mode ...128 12.2 Calculating Actual Resistance ..128 12.3 Digital Rheostat Value Self-programming into the NVM ..129 12.4 Trimming process Using Programmable Trim Block ..132 12.5 Using Chopper ACMP ..138
13 Programmable Delay/Edge Detector .. 139
13.1 Programmable Delay Timing Diagram - Edge Detector Output ...139
14 Additional Logic Function. Deglitch Filter ... 140 15 Voltage Reference .. 141
15.1 Voltage Reference Overview ...141 15.2 Vref Selection Table ..141 15.3 Vref Block Diagram ..143
16 Clocking .. 147
16.1 OSC General Description ...147 16.2 Oscillator0 (2.048 kHz) ...148 16.3 Oscillator1 (2.048 MHz) ...149 16.4 Oscillator2 (25 MHz) ..150 16.5 CNT/DLY Clock Scheme ..150 16.6 External Clocking ...151 16.7 Oscillators Power-On Delay ...152 16.8 Oscillators Accuracy ...152
17 Power-On Reset .. 153
17.1 General Operation ..153 17.2 POR Sequence ..154 17.3 Macrocel s Output States During POR Sequence ...154
18 I
2
C Serial Communications Macrocell .. 157
18.1 I2C Serial Communications Macrocel Overview ..157 18.2 I2C Serial Communications Device Addressing ...157 18.3 I2C Serial General Timing ..158 18.4 I2C Serial Communications Commands ...158 18.5 Chip Configuration Data Protection ..161 18.6 I2C Serial Command Register Map ..162 18.7 I2C Additional Options ..165
19 Non-Volatile Memory .. 167
19.1 Serial NVM Write Operations ...167 19.2 Serial NVM Read Operations ...169 19.3 Serial NVM Erase Operations ..169 19.4 Acknowledge Pol ing ..170 19.5 Low power standby mode ..170 19.6 Emulated EEPROM Write Protection ...170
20 Analog Temperature Sensor ... 172 21 Register Definitions ... 175
21.1 Register Map ..175
22 Package Top Marking System Definition ... 235
22.1 STQFN-24L 3 mm x 3 mm x 0.55 mm, 0.4P FCD Package ..235
23 Package Information .. 236
23.1 Package outlines FOR STQFN 24L 3 mm x 3 mm x 0.55 mm 0.4P Green Package ..236 23.2 STQFN Handling ..236 23.3 Soldering Information ...236
24 Ordering Information ... 237
24.1 Tape and Reel Specifications ..237
25 Layout Guidelines .. 238
25.1 STQFN 24L 3 mm x 3 mm x 0.55 mm 0.4P Green Package ...238
Datasheet Revision 2.1 13-Nov-2020
CFR0011-120-00 3 of 243 © 2020 Dialog Semiconductor Document Outline General Description Key Features Applications 1 Block Diagram 2 Pinout 2.1 Pin Configuration - STQFN-24L 3 Characteristics 3.1 Absolute Maximum Ratings 3.2 Electrostatic Discharge Ratings 3.3 Recommended Operating Conditions 3.4 Electrical Characteristics 3.5 Timing Characteristics 3.6 Oscillator Characteristics 3.6.1 OSC Power-On Delay 3.7 ACMP Characteristics 3.8 Internal Vref Characteristics 3.9 Output Buffers Characteristics 3.10 Analog Temperature Sensor Characteristics 3.11 Programmable Operational Amplifier Characteristics 3.12 100K Digital Rheostat Characteristics 3.13 Analog Switches Characteristics 4 User Programmability 5 IO Pins 5.1 GPIO Pins 5.2 GPI Pins 5.3 Pull-Up/Down Resistors 5.4 Fast Pull-Up/Down during Power-Up 5.5 I2C Mode IO Structure 5.5.1 I2C Mode Structure (for SCL and SDA) 5.6 Matrix OE IO Structure 5.7 GPI Structure 5.7.1 GPI Structure (for I0) 5.8 IO Pins Typical Performance 6 Connection Matrix 6.1 Matrix Input Table 6.2 Matrix Output Table 6.3 Connection Matrix Virtual Inputs 6.4 Connection Matrix Virtual Outputs 7 Combination Function Macrocells 7.1 2-Bit LUT or D Flip-Flop Macrocells 7.1.1 2-Bit LUT or D Flip-Flop Macrocell Used as 2-Bit LUT 7.1.2 Initial Polarity Operations 7.2 2-bit LUT or Programmable Pattern Generator 7.2.1 2-Bit LUT or PGen Macrocell Used as 2-Bit LUT 7.3 3-Bit LUT or D Flip-Flop with Set/Reset Macrocells 7.3.1 3-Bit LUT or D Flip-Flop Macrocells Used as 3-Bit LUTs 7.3.2 Initial Polarity Operations 7.4 4-Bit LUT or D Flip-Flop with Set/Reset Macrocell 7.4.1 4-Bit LUT Macrocell Used as 4-Bit LUT 7.5 3-Bit LUT or Pipe Delay/Ripple Counter Macrocell 7.5.1 3-Bit LUT or Pipe Delay Macrocells Used as 3-Bit LUT 8 Multi-Function Macrocells 8.1 3-Bit LUT or DFF/Latch with 8-Bit Counter/Delay Macrocells 8.1.1 3-Bit LUT or 8-Bit CNT/DLY Block Diagrams 8.1.2 3-Bit LUT or CNT/DLYs Used as 3-Bit LUTs 8.2 4-Bit LUT or DFF/Latch with 16-Bit Counter/Delay Macrocell 8.2.1 4-Bit LUT or DFF/LATCH with 16-Bit CNT/DLY Block Diagram 8.2.2 4-Bit LUT or 16-Bit Counter/Delay Macrocells Used as 4-Bit LUTs 8.3 CNT/DLY/FSM Timing Diagrams 8.3.1 Delay Mode CNT/DLY0 to CNT/DLY6 8.3.2 Count Mode (Count Data: 3), Counter Reset (Rising Edge Detect) CNT/DLY0 to CNT/DLY6 8.3.3 One-Shot Mode CNT/DLY0 to CNT/DLY6 8.3.4 Frequency Detection Mode CNT/DLY0 to CNT/DLY6 8.3.5 Edge Detection Mode CNT/DLY1 to CNT/DLY6 8.3.6 Delayed Edge Detection Mode CNT/DLY0 to CNT/DLY6 8.3.7 CNT/FSM Mode CNT/DLY0 8.3.8 Difference in Counter Value for Counter, Delay, One-Shot, and Frequency Detect Modes 8.4 Wake and Sleep Controller 9 Analog Comparators 9.1 Analog Comparators Overview 9.1.1 ACMP0L Block Diagram 9.1.2 ACMP1L Block Diagram 9.2 Chopper Analog Comparator 9.3 ACMP Sampling Mode 9.4 ACMP Typical Performance 10 Programmable Operational Amplifiers 10.1 General Description 10.2 Modes of Operation 10.2.1 Operational Amplifier Mode 10.2.2 Instrumentation Amplifier Mode 10.2.3 Analog Comparator Mode 10.2.4 Voltage Regulator Mode 10.2.5 Current Sink Mode 10.3 Op Amp Typical Performance 11 Analog Switch Macrocell 11.1 Analog Switch General Description 11.2 Half Bridge Mode 12 Digital Rheostats and Programmable Trim Block 12.1 Potentiometer Mode 12.2 Calculating Actual Resistance 12.3 Digital Rheostat Value Self-programming into the NVM 12.4 Trimming process Using Programmable Trim Block 12.4.1 Trimming Process with Auto-Trim Option Enabled 12.4.2 I2C Controlled Trimming Process with Auto-Trim Option Enabled 12.4.3 Changing Rheostat Value Directly via I2C 12.5 Using Chopper ACMP 13 Programmable Delay/Edge Detector 13.1 Programmable Delay Timing Diagram - Edge Detector Output 14 Additional Logic Function. Deglitch Filter 15 Voltage Reference 15.1 Voltage Reference Overview 15.2 Vref Selection Table 15.3 Vref Block Diagram 16 Clocking 16.1 OSC General Description 16.2 Oscillator0 (2.048 kHz) 16.3 Oscillator1 (2.048 MHz) 16.4 Oscillator2 (25 MHz) 16.5 CNT/DLY Clock Scheme 16.6 External Clocking 16.6.1 IO1 Source for Oscillator0 (2.048 kHz) 16.6.2 IO3 Source for Oscillator1 (2.048 MHz) 16.6.3 IO2 Source for Oscillator2 (25 MHz) 16.7 Oscillators Power-On Delay 16.8 Oscillators Accuracy 17 Power-On Reset 17.1 General Operation 17.2 POR Sequence 17.3 Macrocells Output States During POR Sequence 17.3.1 Initialization 17.3.2 Power-Down 18 I2C Serial Communications Macrocell 18.1 I2C Serial Communications Macrocell Overview 18.2 I2C Serial Communications Device Addressing 18.3 I2C Serial General Timing 18.4 I2C Serial Communications Commands 18.4.1 Byte Write Command 18.4.2 Sequential Write Command 18.4.3 Current Address Read Command 18.4.4 Random Read Command 18.4.5 Sequential Read Command 18.4.6 I2C Serial Reset Command 18.5 Chip Configuration Data Protection 18.6 I2C Serial Command Register Map 18.7 I2C Additional Options 18.7.1 Reading Counter Data via I2C 18.7.2 I2C Byte Write Bit Masking 19 Non-Volatile Memory 19.1 Serial NVM Write Operations 19.2 Serial NVM Read Operations 19.3 Serial NVM Erase Operations 19.4 Acknowledge Polling 19.5 Low power standby mode 19.6 Emulated EEPROM Write Protection 20 Analog Temperature Sensor 21 Register Definitions 21.1 Register Map 22 Package Top Marking System Definition 22.1 STQFN-24L 3 mm x 3 mm x 0.55 mm, 0.4P FCD Package 23 Package Information 23.1 Package outlines FOR STQFN 24L 3 mm x 3 mm x 0.55 mm 0.4P Green Package 23.2 STQFN Handling 23.3 Soldering Information 24 Ordering Information 24.1 Tape and Reel Specifications 25 Layout Guidelines 25.1 STQFN 24L 3 mm x 3 mm x 0.55 mm 0.4P Green Package Glossary Revision History