Datasheet ADP1822 (Analog Devices) - 3

Data Sheet ADP1822 SPECIFICATIONS
VVCC = VPVCC = VSHDN = VFREQ = VTRKN = 5 V, SYNC = MAR = MSEL = GND. All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC). TJ = −40°C to +125°C, unless otherwise specified. Typical values are at TA = 25°C.
Table 1. Parameter Conditions Min Typ Max Unit
POWER SUPPLY Input Voltage 3.7 5.5 V Undervoltage Lockout Threshold VVCC rising, TJ = −40°C to +125°C 2.4 2.7 3.0 V VVCC rising, TA = 25°C 2.5 2.7 2.9 V Undervoltage Lockout Hysteresis VVCC 0.1 V Quiescent Current IVCC + IVCC, not switching 1 2 mA Shutdown Current SHDN = GND 10 µA Power Stage Supply Voltage 1.0 24 V ERROR AMPLIFER FB Regulation Voltage TJ = −40°C to +85°C 594 600 606 mV TJ = −40°C to +125°C 588 600 606 mV FB Input Bias Current –100 +1 +100 nA Error Amplifier Open-Loop Voltage Gain 70 dB COMP Output Sink Current 600 µA COMP Output Source Current 110 µA PWM CONTROLLER PWM Peak Ramp Voltage 1.25 V DL Minimum On Time FREQ = VCC (300 kHz) 120 170 220 ns FREQ = VCC (300 kHz), TA=25°C 140 170 200 ns SOFT START SS Pull-Up Resistance SS = GND 95 kΩ SS Pull-Down Resistance VSS = 0.6 V 1.65 2.5 4.2 kΩ OSCILLATOR Oscillator Frequency FREQ = GND 250 310 375 kHz FREQ = VCC 470 570 720 kHz Synchronization Range FREQ = GND 300 600 kHz FREQ = VCC 600 1200 kHz SYNC Minimum Pulse Width 80 ns CURRENT SENSE CSL Threshold Voltage Relative to PGND −30 0 +30 mV CSL Output Current VCSL = 0 V 42 50 54 µA Current Sense Blanking Period 160 ns GATE DRIVERS DH Rise Time CGATE = 3 nF, VDH = VIN, VBST − VSW = 5 V 16 ns DH Fall Time CGATE = 3 nF, VDH = VIN, VBST − VSW = 5 V 12 ns DL Rise Time CGATE = 3 nF, VDL = VIN 19 ns DL Fall Time CGATE = 3 nF, VDL = 0 V 13 ns Driver RON, Sourcing Current 1 A, 0.7 µs pulse 2 Ω Driver RON, Sinking Current 1 A, 0.7 µs pulse 1.5 Ω DL Low to DH High Dead Time 33 ns DH Low to DL High Dead Time 42 ns VOLTAGE MARGINING High Output Voltage Margin Resistance MUP to FB, VMAR = VMSEL = 5 V 20 Ω Low Output Voltage Margin Resistance MDN to FB, VMAR = 5 V, VMSEL = 0 V 20 Ω Rev. D | Page 3 of 24 Document Outline Features Applications General Description Revision History Specifications Absolute Maximum Ratings ESD Caution Simplified Block Diagram Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Current-Limit Scheme Output Voltage Margining Output Voltage Tracking Soft Start High-Side Driver (BST and DH) Low-Side Driver (DL) Input Voltage Range Setting the Output Voltage Switching Frequency Control Compensation Power-Good Indicator Shutdown Control Application Information Selecting the Input Capacitor Output LC Filter Selecting the MOSFETS Setting the Current Limit Feedback Voltage Divider Setting the Voltage Margin Compensating the Regulator Compensation Using the ESR Zero Compensation Using Feed-Forward Compensation Using Both the ESR and Feed-Forward Zeros Setting the Soft Start Period Synchronizing the Converter Setting the Output Voltage Tracking Application Circuits Outline Dimensions Ordering Guide