Datasheet ADP1864 (Analog Devices) - 5
| Hersteller | Analog Devices |
| Beschreibung | Constant Frequency Current-Mode Step-Down DC-to-DC Controller in TSOT |
| Seiten / Seite | 16 / 5 — Data Sheet. ADP1864. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. COMP. … |
| Revision | C |
| Dateiformat / Größe | PDF / 240 Kb |
| Dokumentensprache | Englisch |
Data Sheet. ADP1864. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. COMP. PGATE. GND. TOP VIEW. (Not to Scale)
Modelllinie für dieses Datenblatt
Textversion des Dokuments
link to page 12
Data Sheet ADP1864 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS COMP 1 6 PGATE ADP1864 GND 2 TOP VIEW 5 IN (Not to Scale)
003
FB 3 4 CS
05562- Figure 2. Pin Configuration
Table 3. Pin Function Descriptions Pin No. Mnemonic Description
1 COMP Regulator Compensation Node. COMP is the output of the internal transconductance error amplifier. Connect a series RC from COMP to GND to compensate for the control loop. Add an extra high frequency capacitor between COMP and GND to further reduce switching jitter. The value of this is typically one-tenth of the main compensation capacitor. Pulling the COMP pin below 0.3 V disables the ADP1864 and turns off the external PFET. 2 GND Analog Ground. Directly connect the compensation and feedback networks to GND, preferably with a small analog GND plane. Connect GND to the power ground (PGND) plane with a narrow track at a single point close to the GND pin. See the Layout Considerations section for more information. 3 FB Feedback Input. Connect a resistive voltage divider from the output voltage to FB to set the output voltage. The regulation feedback voltage is 0.8 V. Place the feedback resistors as close as possible to the FB pin. 4 CS Current Sense Input. CS is the negative input of the current sense amplifier. It provides the current feedback signal used to terminate the PWM on time. Place a current sense resistor between IN and CS to set the current limit. The current limit threshold is typically 125 mV. 5 IN Power Input. IN is the power supply to the ADP1864 and the positive input of the current sense amplifier. Connect IN to the positive side of the input voltage source. Bypass IN to PGND with a 10 μF or larger capacitor as close as possible to the ADP1864. For additional high frequency noise reduction, add a 0.1 μF capacitor to PGND at the IN pin. 6 PGATE Gate Drive Output. PGATE drives the gate of the external P-channel MOSFET. Connect PGATE to the gate of the external MOSFET. Rev. C | Page 5 of 16 Document Outline Features Applications General Description Typical Applications Diagram Revision History Specifications Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Loop Startup Short-Circuit Protection Undervoltage Lockout (UVLO) Overvoltage Lockout Protection (OVP) Soft Start Applications Information ADIsimPower Design Tool Duty Cycle Ripple Current Sense Resistor Inductor Value MOSFET Diode Input Capacitor Output Capacitor Feedback Resistors Layout Considerations Example Applications Circuits Outline Dimensions Ordering Guide
Data Sheet ADP1864 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS COMP 1 6 PGATE ADP1864 GND 2 TOP VIEW 5 IN (Not to Scale)
003
FB 3 4 CS
05562- Figure 2. Pin Configuration
Table 3. Pin Function Descriptions Pin No. Mnemonic Description
1 COMP Regulator Compensation Node. COMP is the output of the internal transconductance error amplifier. Connect a series RC from COMP to GND to compensate for the control loop. Add an extra high frequency capacitor between COMP and GND to further reduce switching jitter. The value of this is typically one-tenth of the main compensation capacitor. Pulling the COMP pin below 0.3 V disables the ADP1864 and turns off the external PFET. 2 GND Analog Ground. Directly connect the compensation and feedback networks to GND, preferably with a small analog GND plane. Connect GND to the power ground (PGND) plane with a narrow track at a single point close to the GND pin. See the Layout Considerations section for more information. 3 FB Feedback Input. Connect a resistive voltage divider from the output voltage to FB to set the output voltage. The regulation feedback voltage is 0.8 V. Place the feedback resistors as close as possible to the FB pin. 4 CS Current Sense Input. CS is the negative input of the current sense amplifier. It provides the current feedback signal used to terminate the PWM on time. Place a current sense resistor between IN and CS to set the current limit. The current limit threshold is typically 125 mV. 5 IN Power Input. IN is the power supply to the ADP1864 and the positive input of the current sense amplifier. Connect IN to the positive side of the input voltage source. Bypass IN to PGND with a 10 μF or larger capacitor as close as possible to the ADP1864. For additional high frequency noise reduction, add a 0.1 μF capacitor to PGND at the IN pin. 6 PGATE Gate Drive Output. PGATE drives the gate of the external P-channel MOSFET. Connect PGATE to the gate of the external MOSFET. Rev. C | Page 5 of 16 Document Outline Features Applications General Description Typical Applications Diagram Revision History Specifications Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Loop Startup Short-Circuit Protection Undervoltage Lockout (UVLO) Overvoltage Lockout Protection (OVP) Soft Start Applications Information ADIsimPower Design Tool Duty Cycle Ripple Current Sense Resistor Inductor Value MOSFET Diode Input Capacitor Output Capacitor Feedback Resistors Layout Considerations Example Applications Circuits Outline Dimensions Ordering Guide