Datasheet ADP1870, ADP1871 (Analog Devices) - 6

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ADP1870/ADP1871 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS VIN 1 10 BST COMP/EN 2 ADP1870/ 9 SW ADP1871 FB 3 8 DRVH TOP VIEW GND 4 7 PGND (Not to Scale) VREG 5 6 DRVL NOTES
003
1. THE EXPOSED PAD MUST BE CONNECTED TO GROUND.
08730- Figure 3. Pin Configuration
Table 4. Pin Function Descriptions Pin No. Mnemonic Description
1 VIN High Input Voltage. Connect VIN to the drain of the upper-side MOSFET. 2 COMP/EN Output of the Internal Error Amplifier/IC Enable. When this pin functions as EN, applying 0 V to this pin disables the IC. 3 FB Noninverting Input of the Internal Error Amplifier. This is the node where the feedback resistor is connected. 4 GND Analog Ground Reference Pin of the IC. All sensitive analog components should be connected to this ground plane (see the Layout Considerations section). 5 VREG Internal Regulator Supply Bias Voltage for the ADP1870/ADP1871 Controller (Includes the Output Gate Drivers). A bypass capacitor of 1 µF directly from this pin to PGND and a 0.1 µF across VREG and GND are recommended. VREG should not be loaded externally because it is intended to only bias internal circuitry. 6 DRVL Drive Output for the External Lower-Side, N-Channel MOSFET. This pin also serves as the current-sense gain setting pin (see Figure 69). 7 PGND Power GND. Ground for the lower-side gate driver and lower-side, N-channel MOSFET. 8 DRVH Drive Output for the External Upper-Side, N-Channel MOSFET. 9 SW Switch Node Connection. 10 BST Bootstrap for the Upper-Side MOSFET Gate Drive Circuitry. An internal boot rectifier (diode) is connected between VREG and BST. A capacitor from BST to SW is required. An external Schottky diode can also be connected between VREG and BST for increased gate drive capability. Rev. B | Page 6 of 44 Document Outline Features Applications General Description Typical Applications Circuit Revision History Specifications Absolute Maximum Ratings Thermal Resistance Boundary Condition ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics ADP1870/ADP1871 Block Diagram Theory of Operation Startup Soft Start Precision Enable Circuitry Undervoltage Lockout On-Board Low Dropout Regulator Thermal Shutdown Programming Resistor (RES) Detect Circuit Valley Current-Limit Setting Hiccup Mode During Short Circuit Synchronous Rectifier Power Saving Mode (PSM) Version (ADP1871) Timer Operation Pseudo-Fixed Frequency Applications Information Feedback Resistor Divider Inductor Selection Output Ripple Voltage (ΔVRR) Output Capacitor Selection Compensation Network Output Filter Impedance (ZFILT) Error Amplifier Output Impedance (ZCOMP) Error Amplifier Gain (GM) Current-Sense Loop Gain (GCS) Crossover Frequency Efficiency Considerations Channel Conduction Loss MOSFET Driver Loss Switching Loss Diode Conduction Loss Inductor Loss Input Capacitor Selection Thermal Considerations Design Example Input Capacitor Inductor Current Limit Programming Output Capacitor Feedback Resistor Network Setup Compensation Network Loss Calculations External Component Recommendations Layout Considerations IC Section (Left Side of Evaluation Board) Power Section Differential Sensing Typical Applications Circuits 15 A, 300 kHz High Current Application Circuit 5.5 V Input, 600 kHz Application Circuit 300 kHz High Current Application Circuit Outline Dimensions Ordering Guide