Datasheet ADP1851 (Analog Devices) - 5

Data Sheet ADP1851 Parameter Symbol Test Conditions/Comments Min Typ Max Unit
SYNC Logic Input Low 1.3 V SYNC Logic Input High 1.9 V SYNC Input Pull-Down Resistance RSYNC 1 MΩ GATE DRIVERS DH Rise Time CDH = 3 nF, VBST − VSW = 5 V 16 ns DH Fall Time CDH = 3 nF, VBST − VSW = 5 V 14 ns DL Rise Time CDL = 3 nF 16 ns DL Fall Time CDL = 3 nF 14 ns DH to DL Dead Time External 3 nF connected to DH and DL 25 ns DH or DL Driver RON, Sourcing RON_SOURCE Sourcing 2 A with a 100 ns pulse 2 Ω Current1 Sourcing 1 A with a 100 ns pulse, VIN = 3 V 2.3 Ω DH or DL Driver RON, Tempco TCRON VIN = 3 V or 12 V 0.3 %/°C DH or DL Driver RON, Sinking RON_SINK Sinking 2 A with a 100 ns pulse 1.5 Ω Current1 Sinking 1 A with a 100 ns pulse, VIN = 3 V 2 Ω DH Maximum Duty Cycle1 fOSC = 300 kHz 90 % fOSC = 1500 kHz 50 % Minimum DH On Time fOSC = 200 kHz to 1500 kHz 85 ns Minimum DH Off Time fOSC = 200 kHz to 1500 kHz 345 ns Minimum DL On Time fOSC = 200 kHz to 1500 kHz 295 ns COMP VOLTAGE RANGE COMP Pulse Skip Threshold VCOMP,THRES In pulse skip mode (PSM) 0.9 V COMP Clamp High Voltage VCOMP,HIGH 2.2 V THERMAL SHUTDOWN Thermal Shutdown Threshold TTMSD 155 °C Thermal Shutdown Hysteresis 20 °C OVERVOLTAGE AND POWER-GOOD THRESHOLDS FB Overvoltage Threshold VOV VFB rising 0.630 0.65 0.670 V FB Overvoltage Hysteresis 18 mV FB Undervoltage Threshold VUV VFB falling 0.525 0.55 0.575 V FB Undervoltage Hysteresis 15 mV SOFT START/TRACK SS/TRK Output Current ISS During startup 4.6 6.5 8.4 µA SS/TRK Pull-Down Resistor During a fault condition 3 kΩ SS/TRK Input Voltage Range1 0 5 V FB to SS/TRK Offset VSS/TRK = 0.1 V to 0.6 V; offset = VFB − VSS/TRK −10 +10 mV PGOOD PGOOD Pull-Up Resistor RPGOOD Internal pull-up resistor to VCCO 12.5 kΩ PGOOD Delay 12 µs Overvoltage or Undervoltage Minimum duration required to trigger the 10 µs Minimum Duration PGOOD signal ILIM Threshold Voltage1 Relative to PGND −5 0 +5 mV ILIM Output Current ILIM = PGND 45 50 55 µA Current Sense Blanking Period After DL goes high; current limit is not sensed 100 ns during this period INTEGRATED RECTIFIER At 20 mA forward current 16 Ω (BOOST DIODE) RESISTANCE ZERO CURRENT CROSS OFFSET In pulse skip mode only; fOSC = 300 kHz 0 2 4 mV (SW TO PGND)1 1 Guaranteed by design. 2 Connect VIN to VCCO when VIN < 5.5 V. Rev. B | Page 5 of 24 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TYPICAL OPERATION CIRCUIT REVISION HISTORY SIMPLIFIED BLOCK DIAGRAM SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION CONTROL ARCHITECTURE OSCILLATOR FREQUENCY SYNCHRONIZATION PWM AND PULSE SKIP MODES OF OPERATION SYNCHRONOUS RECTIFIER AND DEAD TIME INPUT UNDERVOLTAGE LOCKOUT INTERNAL LINEAR REGULATOR OVERVOLTAGE PROTECTION POWER GOOD SHORT-CIRCUIT AND CURRENT-LIMIT PROTECTION ENABLE/DISABLE CONTROL THERMAL OVERLOAD PROTECTION APPLICATIONS INFORMATION ADIsimPower DESIGN TOOL SETTING THE OUTPUT VOLTAGE SOFT START SETTING THE CURRENT LIMIT ACCURATE CURRENT-LIMIT SENSING INPUT CAPACITOR SELECTION VIN PIN FILTER BOOST CAPACITOR SELECTION INDUCTOR SELECTION OUTPUT CAPACITOR SELECTION MOSFET SELECTION LOOP COMPENSATION—VOLTAGE MODE Type III Compensation LOOP COMPENSATION—CURRENT MODE Setting the Slope Compensation Setting the Current Sense Gain Type II Compensation SWITCHING NOISE AND OVERSHOOT REDUCTION VOLTAGE TRACKING Coincident Tracking Ratiometric Tracking PCB LAYOUT GUIDELINES TYPICAL OPERATING CIRCUITS OUTLINE DIMENSIONS ORDERING GUIDE