Datasheet LTC7810 (Analog Devices) - 10

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PIN FUNCTIONS DRVSET (Pin 2):
DRVCC Regulation Program Pin. This duty cycle of 3.3%. This pin sources 10μA of current when pin sets the regulation point for the DRVCC low dropout EXTVCC is below the switchover voltage and the LTC7810 (LDO) linear regulators. Tying this pin to GND sets DRVCC is not in sleep, and sinks 10μA when EXTVCC is above to 8V, tying it to INTVCC sets DRVCC to 6V, and float- the switchover voltage or when the LTC7810 is in sleep. ing this pin sets DRVCC to 10V. The DRVCC UVLO and Ground this pin to disable the regulator shutdown timer. EXTVCC switchover thresholds change correspondingly
MODE (Pin 8):
Mode Select and Burst Clamp Adjust Input. with the DRVCC regulation point, as listed in the Electrical This input determines how the LTC7810 operates at light Characteristics table. loads. Pulling this pin to ground selects Burst Mode oper-
INTVCC (Pin 3):
Output of the Internal 4.5V Low Dropout ation with a burst clamp level of 25% of VSENSE(MAX). Regulator. Internal low voltage analog and digital circuits Tying this pin to a voltage between 0.5V and 1V selects are powered by this supply. A low ESR 0.1µF ceramic Burst Mode and adjusts the burst clamp level between bypass capacitor should be connected between INTVCC 10% and 60%. Tying this pin to INTVCC forces continu- and GND, as close as possible to the IC. ous inductor current operation. Tying this pin to a voltage
PLLIN/SPREAD (Pin 4):
External Synchronization Input greater than 1.4V and less than INTVCC – 1.3V selects to Phase Detector and Spread Spectrum Enable. When an pulse-skipping operation. Do not float this pin. external clock is applied to this pin, the phase-locked loop
OVLO (Pin 9):
Overvoltage Lockout Input. Forcing this will force the rising TG1 signal to be synchronized with the pin above 1.22V disables switching of the controllers. rising edge of the external clock. When not synchroniz- The DRVCC and INTVCC regulation is maintained during ing to an external clock, tie this input to INTVCC to enable an OVLO event. Exceeding the OVLO threshold triggers a spread spectrum dithering of the oscillator or to ground soft-start reset. Tie this pin to ground if the OVLO func- to disable spread spectrum. tion is not used.
SGND (Pins 5, Exposed Pad Pin 49):
Small-signal ground
NDRV (Pin 10):
Drive Output for External Pass Device common to both controllers, must be routed separately of the NDRV LDO Regulator for DRVCC. Connect this pin from high current grounds to the common (–) terminals to the gate of an external NMOS pass device. An internal of the CIN capacitors. The exposed pad must be soldered charge pump allows NDRV to be driven above VIN for low to PCB ground for rated thermal performance. dropout performance. Tie this pin to DRVCC if the NDRV
FREQ (Pin 6):
Frequency Control Pin for the Internal VCO. regulator is not used. Connecting the pin to GND forces the VCO to a fixed low
EXTVCC (Pin 11):
External Power Input to an Internal LDO frequency of 200kHz. Connecting the pin to INTVCC forces Connected to DRVCC. This LDO supplies DRVCC power, the VCO to a fixed high frequency of 300kHz. Other fre- bypassing both the internal VIN LDO and the external quencies between 50kHz and 750kHz can be programmed NDRV LDO whenever EXTVCC is higher than its switcho- using a resistor between FREQ and GND. The resistor and ver threshold. See DRVCC Regulators in the Applications an internal 20µA source current create a voltage used by Information section. Do not exceed 65V on this pin. the internal oscillator to set the frequency. Connect this pin to ground if the EXTVCC LDO is not used.
REGSD (Pin 7):
Regulator Shutdown Timer. This pin limits
SENSE1–, SENSE2– (Pins 1, 12):
The (–) Input to the the time allowed for switching while the internal VIN or Differential Current Comparators. When SENSE1,2– is NDRV linear regulators are operating, due to EXTVCC being greater than INTVCC, the SENSE– pin supplies current to below its switchover voltage. A capacitor from REGSD the current comparator. When SENSE1– is greater than to ground limits the time to tREGSD = 1.2•CREGSD/10µA. 3.2V, it supplies the majority of the sleep mode quiescent When the REGSD voltage exceeds 1.2V, the linear regu- current instead of VIN, further reducing the input-referred lator shuts down for 29 • tREGSD, giving a “regulator-on” quiescent current. Rev. A 10 For more information www.analog.com Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Pin Configuration Electrical Characteristics Typical Performance Characteristics Pin Functions Functional Diagram Operation Main Control Loop Power and Bias Supplies (VIN, NDRV, EXTVCC, DRVCC, REGSD) Boost Supply and Dropout (BOOST and SW pins) Start-Up and Shutdown (RUN, TRACK/SS, OVLO Pins) Light Load Operation: Burst Mode Operation, Pulse Skipping or Forced Continuous Mode (MODE Pin) Frequency Selection, Spread Spectrum, and Phase-Locked Loop (FREQ and PLLIN/SPREAD Pins) Applications Information Current Sense Selection Low Value Resistor Current Sensing Inductor DCR Sensing Setting the Operating Frequency Selecting the Light-Load Operating Mode Inductor Value Calculation Inductor Core Selection Power MOSFET Selection CIN and COUT Selection Setting the Output Voltage RUN Pins and Overvoltage/Undervoltage Lockout Tracking and Soft-Start (TRACK/SS1, TRACK/SS2 Pins) Single Output Two-Phase Operation DRVCC Regulators Topside MOSFET Driver Supply (CB, DB) Burst Clamp Programming Fault Conditions: Current Limit and Current Foldback Fault Conditions: Overvoltage Protection (Crowbar) Fault Conditions: Overtemperature Protection Phase-Locked Loop and Frequency Synchronization Minimum On-Time Considerations Efficiency Considerations Checking Transient Response Design Example PC Board Layout Checklist PC Board Layout Debugging Typical Applications Package Description Revision History Typical Application Related Parts