Datasheet LTC7802-3.3 (Analog Devices) - 9
| Hersteller | Analog Devices |
| Beschreibung | 40V Low IQ, 3MHz Dual, 2-Phase Synchronous Step-Down Controller with Spread Spectrum |
| Seiten / Seite | 34 / 9 — PIN FUNCTIONS. SENSE1+, SENSE2+ (Pins 1,8):. EXTVCC (Pin 18):. SENSE1–, … |
| Dateiformat / Größe | PDF / 1.5 Mb |
| Dokumentensprache | Englisch |
PIN FUNCTIONS. SENSE1+, SENSE2+ (Pins 1,8):. EXTVCC (Pin 18):. SENSE1–, SENSE2– (Pins 2,7):. VIN (Pin 19):
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link to page 23 link to page 15 LTC7802-3.3
PIN FUNCTIONS SENSE1+, SENSE2+ (Pins 1,8):
The Positive (+) Input
EXTVCC (Pin 18):
External Power Input to an Internal LDO to the Differential Current Comparators. The ITH pin Connected to INTVCC. This LDO supplies INTVCC power, voltage and controlled offsets between the SENSE– and bypassing the internal LDO powered from VIN whenever SENSE+ pins in conjunction with RSENSE set the current EXTVCC is higher than 4.7V. See INTVCC Regulators in the trip threshold. Applications Information section. Do not exceed 30V on
SENSE1–, SENSE2– (Pins 2,7):
The Negative (–) Input this pin. Connect this pin to ground if the EXTVCC LDO to the Differential Current Comparators. The SENSE2– is not used. pin supplies current to its current comparator when it is
VIN (Pin 19):
Main Bias Input Supply Pin. A bypass capac- greater than INTVCC. When SENSE1– is 3.2V or greater, itor should be tied between this pin and GND. it supplies the majority of the sleep mode quiescent cur-
PLLIN/SPREAD (Pin 25):
External Synchronization Input rent instead of VIN, further reducing the input-referred and Spread Spectrum Selection. When an external clock quiescent current. is applied to this pin, the phase-locked loop will force the
FREQ (Pin 3):
Frequency Control Pin for the Internal rising TG1 signal to be synchronized with the rising edge Oscillator. Connect to ground to set the switching fre- of the external clock. When an external clock is present, the quency to 350kHz. Connect to INTVCC to set the switching regulators operate in pulse-skipping mode if it is selected frequency to 2.25MHz. Frequencies between 100kHz and by the MODE pin, or in forced continuous mode otherwise. 3MHz can be programmed using a resistor between the When not synchronizing to an external clock, tie this input FREQ pin and ground. Minimize the capacitance on this pin. to INTVCC to enable spread spectrum dithering of the oscil-
MODE (Pin 4):
Mode Select Input. This input, which acts lator or to ground to disable spread spectrum. on both channels, determines how the LTC7802-3.3 oper-
BG1, BG2 (Pins 20,16):
High Current Gate Drives for ates at light loads. Pulling this pin to ground selects Burst Bottom (Synchronous) N-Channel MOSFETs. Voltage Mode operation. An internal 100k resistor to ground also swing at these pins is from ground to INTVCC. invokes Burst Mode operation when the pin is floating.
BOOST1, BOOST2 (Pins 21,15):
Bootstrapped Supplies to Tying this pin to INTVCC forces continuous inductor cur- the Top Side Floating Drivers. Connect capacitors between rent operation. Tying this pin to INTVCC through a 100k the corresponding BOOST and SW pins for each channel. resistor selects pulse-skipping operation. Also connect Schottky diodes between the BOOST1 and
RUN1, RUN2 (Pins 5,6):
Run Control Inputs for Each INTVCC pins and the BOOST2 and INTVCC pins. Voltage Controller. Forcing either of these pins below 1.1V disables swing at the BOOST pins is from INTVCC to (VIN + INTVCC). switching of the corresponding controller. Forcing both of
SW1, SW2 (Pins 22,14):
Switch Node Connections to these pins below 0.7V shuts down the entire LTC7802- Inductors. 3.3, reducing quiescent current to approximately 1.5µA. These pins can be tied to VIN for always-on operation. Do
TG1, TG2 (Pins 23,13):
High Current Gate Drives for Top not float the RUN pins. N Channel MOSFETs. These are the outputs of floating drivers with a voltage swing of INTV
INTV
CC superimposed on
CC (Pin 17):
Output of the Internal 5.1V Low Dropout the switch node voltage SW. Regulator. The driver and control circuits are powered by this supply. Must be decoupled to ground with a minimum
PGOOD1, PGOOD2 (Pins 24,12):
Open-Drain Power of 4.7μF ceramic or tantalum capacitor. Good Outputs. The VOUT1, VFB2 pins are monitored to ensure that VOUT1,2 are in regulation. When VOUT is not Rev. 0 For more information www.analog.com 9 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Pin Configuration Electrical Characteristics Typical Performance Characteristics Pin Functions Functional Diagram Operation Applications Information Typical Applications Package Description Typical Application Related Parts
PIN FUNCTIONS SENSE1+, SENSE2+ (Pins 1,8):
The Positive (+) Input
EXTVCC (Pin 18):
External Power Input to an Internal LDO to the Differential Current Comparators. The ITH pin Connected to INTVCC. This LDO supplies INTVCC power, voltage and controlled offsets between the SENSE– and bypassing the internal LDO powered from VIN whenever SENSE+ pins in conjunction with RSENSE set the current EXTVCC is higher than 4.7V. See INTVCC Regulators in the trip threshold. Applications Information section. Do not exceed 30V on
SENSE1–, SENSE2– (Pins 2,7):
The Negative (–) Input this pin. Connect this pin to ground if the EXTVCC LDO to the Differential Current Comparators. The SENSE2– is not used. pin supplies current to its current comparator when it is
VIN (Pin 19):
Main Bias Input Supply Pin. A bypass capac- greater than INTVCC. When SENSE1– is 3.2V or greater, itor should be tied between this pin and GND. it supplies the majority of the sleep mode quiescent cur-
PLLIN/SPREAD (Pin 25):
External Synchronization Input rent instead of VIN, further reducing the input-referred and Spread Spectrum Selection. When an external clock quiescent current. is applied to this pin, the phase-locked loop will force the
FREQ (Pin 3):
Frequency Control Pin for the Internal rising TG1 signal to be synchronized with the rising edge Oscillator. Connect to ground to set the switching fre- of the external clock. When an external clock is present, the quency to 350kHz. Connect to INTVCC to set the switching regulators operate in pulse-skipping mode if it is selected frequency to 2.25MHz. Frequencies between 100kHz and by the MODE pin, or in forced continuous mode otherwise. 3MHz can be programmed using a resistor between the When not synchronizing to an external clock, tie this input FREQ pin and ground. Minimize the capacitance on this pin. to INTVCC to enable spread spectrum dithering of the oscil-
MODE (Pin 4):
Mode Select Input. This input, which acts lator or to ground to disable spread spectrum. on both channels, determines how the LTC7802-3.3 oper-
BG1, BG2 (Pins 20,16):
High Current Gate Drives for ates at light loads. Pulling this pin to ground selects Burst Bottom (Synchronous) N-Channel MOSFETs. Voltage Mode operation. An internal 100k resistor to ground also swing at these pins is from ground to INTVCC. invokes Burst Mode operation when the pin is floating.
BOOST1, BOOST2 (Pins 21,15):
Bootstrapped Supplies to Tying this pin to INTVCC forces continuous inductor cur- the Top Side Floating Drivers. Connect capacitors between rent operation. Tying this pin to INTVCC through a 100k the corresponding BOOST and SW pins for each channel. resistor selects pulse-skipping operation. Also connect Schottky diodes between the BOOST1 and
RUN1, RUN2 (Pins 5,6):
Run Control Inputs for Each INTVCC pins and the BOOST2 and INTVCC pins. Voltage Controller. Forcing either of these pins below 1.1V disables swing at the BOOST pins is from INTVCC to (VIN + INTVCC). switching of the corresponding controller. Forcing both of
SW1, SW2 (Pins 22,14):
Switch Node Connections to these pins below 0.7V shuts down the entire LTC7802- Inductors. 3.3, reducing quiescent current to approximately 1.5µA. These pins can be tied to VIN for always-on operation. Do
TG1, TG2 (Pins 23,13):
High Current Gate Drives for Top not float the RUN pins. N Channel MOSFETs. These are the outputs of floating drivers with a voltage swing of INTV
INTV
CC superimposed on
CC (Pin 17):
Output of the Internal 5.1V Low Dropout the switch node voltage SW. Regulator. The driver and control circuits are powered by this supply. Must be decoupled to ground with a minimum
PGOOD1, PGOOD2 (Pins 24,12):
Open-Drain Power of 4.7μF ceramic or tantalum capacitor. Good Outputs. The VOUT1, VFB2 pins are monitored to ensure that VOUT1,2 are in regulation. When VOUT is not Rev. 0 For more information www.analog.com 9 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Pin Configuration Electrical Characteristics Typical Performance Characteristics Pin Functions Functional Diagram Operation Applications Information Typical Applications Package Description Typical Application Related Parts