Datasheet OP07 (Analog Devices)

Ultralow Offset Voltage Operational Amplifier Data Sheet OP07 FEATURES PIN CONFIGURATION Low VOS: 75 μV maximum Low V V 1 OS TRIM 8 VOS TRIM OS drift: 1.3 μV/°C maximum OP07 Ultrastable vs. time: 1.5 μV per month maximum –IN 2 7 V+ Low noise: 0.6 μV p-p maximum +IN 3 6 OUT Wide input voltage range: ±14 V typical V– 4 5 NC Wide supply voltage range: ±3 V to ±18 V
001
NC = NO CONNECT 125°C temperature-tested dice
00316- Figure 1.
APPLICATIONS Wireless base station control circuits Optical network control circuits
The wide input voltage range of ±13 V minimum combined
Instrumentation
with a high CMRR of 106 dB (OP07E) and high input
Sensors and controls
impedance provide high accuracy in the noninverting circuit
Thermocouples
configuration. Excellent linearity and gain accuracy can be
Resistor thermal detectors (RTDs)
maintained even at high closed-loop gains. Stability of offsets
Strain bridges
and gain with time or variations in temperature is excellent. The
Shunt current measurements
accuracy and stability of the OP07, even at high gain, combined
Precision filters
with the freedom from external nulling have made the OP07 an industry standard for instrumentation applications.
GENERAL DESCRIPTION
The OP07 is available in two standard performance grades. The The OP07 has very low input offset voltage (75 μV maximum for OP07E is specified for operation over the 0°C to 70°C range, OP07E) that is obtained by trimming at the wafer stage. These and the OP07C is specified over the −40°C to +85°C low offset voltages general y eliminate any need for external temperature range. nul ing. The OP07 also features low input bias current (±4 nA for the OP07E) and high open-loop gain (200 V/mV for the OP07E). The OP07 is available in epoxy 8-lead PDIP and 8-lead narrow The low offset and high open-loop gain make the OP07 SOIC packages. For CERDIP and TO-99 packages and standard particularly useful for high gain instrumentation applications. microcircuit drawing (SMD) versions, see the OP77.
V+ 7 R2A1 R2B1 (OPTIONAL C1 R7 NULL) 1 8 R1A R1B Q19 Q9 Q10 R9 Q11 Q8 Q12 OUT Q7 6 Q5 Q3 Q6 Q4 R3 C3 Q27 C2 Q17 R10 NONINVERTING Q16 INPUT 3 Q1 R5 Q21 Q23 Q26 Q20 R4 Q22 Q24 Q15 INVERTING Q2 Q25 INPUT 2 Q14 Q18 Q13 R6 R8 4 V–
002
1 R2A AND R2B ARE ELECTRONICALLY ADJUSTED ON CHIP AT FACTORY FOR MINIMUM INPUT OFFSET VOLTAGE.
00316- Figure 2. Simplified Schematic
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Document Outline Features Applications General Description Pin Configuration Revision History Specifications OP07E Electrical Characteristics OP07C Electrical Characteristics Absolute Maximum Ratings Thermal Resistance ESD Caution Typical Performance Characteristics Typical Applications Applications Information Outline Dimensions Ordering Guide