Data SheetAD80992090–30G = +55pF, CSP19 VS = ±5V80–4518MAGNITUDE70–601760–751650–9015PHASE40–105141pF, SOIC30–1201320–135121pF, CSPOPEN-LOOP GAIN (dB)CLOSED-LOOP GAIN (dB)1110–150OPEN-LOOP PHASE (Degrees)VS = ±5V105pF, SOIC0–165RL = 1k Ω UNCOMPENSATED9–10–18011010010000.0010.010.11.0101001000FREQUENCY (MHz) 04511-0-104 FREQUENCY (MHz) 04511-0-080 Figure 11. Small Signal Frequency Response for Various Capacitive Loads Figure 14. Open Loop Frequency Response 12G = +2G = +10G = +201–10G = +10–2–1G = +20–3–2G = +20–4–3–5G = +5–4–6–5–7–6G = +5–8–7VS = ±5VVS = ±5VNORMALIZED CLOSED-LOOP GAIN (dB)–9 VOUT = 2V p-pNORMALIZED CLOSED-LOOP GAIN (dB)–8 VOUT = 2V p-pRLOAD = 1k Ω RLOAD = 1k Ω –10–911010010001101001000FREQUENCY (MHz)FREQUENCY (MHz) 04511-0-011 04511-0-012 Figure 12. Large Signal Frequency Response for Various Gains (SOIC) Figure 15. Large Signal Frequency Response for Various Gains (LFCSP) 6.56.5VVS = ±5VOUT = 1.4V p-pVVS = ±5VOUT = 1.4V p-pG = +2G = +26.46.4RL = 150 Ω RL = 150 Ω 6.36.36.26.26.16.16.06.05.95.9VOUT = 200mV p-p5.8VOUT = 200mV p-p5.8CLOSED-LOOP GAIN (dB)CLOSED-LOOP GAIN (dB)5.75.75.65.65.55.5110100110100FREQUENCY (MHz)FREQUENCY (MHz) 04511-0-009 04511-0-008 Figure 13. 0.1 dB Flatness (SOIC) Figure 16. 0.1 dB Flatness (LFCSP) Rev. E | Page 7 of 26 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION CONNECTION DIAGRAMS REVISION HISTORY SPECIFICATIONS SPECIFICATIONS WITH ±5 V SUPPLY SPECIFICATIONS WITH +5 V SUPPLY ABSOLUTE MAXIMUM RATINGS MAXIMUM POWER DISSIPATION ESD CAUTION TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION APPLICATIONS INFORMATION USING THE AD8099 CIRCUIT COMPONENTS RECOMMENDED VALUES CIRCUIT CONFIGURATIONS PERFORMANCE vs. COMPONENT VALUES TOTAL OUTPUT NOISE CALCULATIONS AND DESIGN INPUT BIAS CURRENT AND DC OFFSET PIN AND INPUT BIAS CANCELLATION 16-BIT ADC DRIVER CIRCUIT CONSIDERATIONS PCB Layout Parasitics Grounding Power Supply Bypassing Component Selection DESIGN TOOLS AND TECHNICAL SUPPORT OUTLINE DIMENSIONS ORDERING GUIDE