Datasheet ADA4350 (Analog Devices) - 7

HerstellerAnalog Devices
BeschreibungFET Input Analog Front End with ADC Driver
Seiten / Seite37 / 7 — Data Sheet. ADA4350. Parameter. Test Conditions/Comments1. Min. Typ. Max …
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DokumentenspracheEnglisch

Data Sheet. ADA4350. Parameter. Test Conditions/Comments1. Min. Typ. Max Unit

Data Sheet ADA4350 Parameter Test Conditions/Comments1 Min Typ Max Unit

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Data Sheet ADA4350 Parameter Test Conditions/Comments1 Min Typ Max Unit
OUTPUT CHARACTERISTICS Output Voltage Swing RL = no load, single-ended ±4.8 ±4.83 V RL = 500 Ω, single-ended ±4.55 ±4.6 V Output Common-Mode Voltage Range −5 +3.8 V Linear Output Current P1 or M1, VOUT = 2 V p-p, 60 dB SFDR 18 mA rms Differential output, VOUT = 4 V p-p, 60 dB SFDR 18 mA rms Short Circuit Current P1 or M1, sinking/sourcing 43/76 mA Capacitive Load Drive When used differential y at each VOUTx, 30% overshoot, 33 pF VOUT = 200 mV p-p When P1/M1 is used, 30% overshoot, VOUT = 100 mV p-p 47 pF POWER SUPPLY Operating Range 3.3 12 V Positive Power Supply Rejection Ratio For P1 90 106 dB For M1 86 100 dB Negative Power Supply Rejection Ratio For P1 80 100 dB For M1 78 90 dB 1 P1 and M1 within this table refer to the amplifiers shown in Figure 1. Rev. B | Page 7 of 37 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM REVISION HISTORY SPECIFICATIONS ±5 V FULL SYSTEM ±5 V FET INPUT AMPLIFIER ±5 V INTERNAL SWITCHING NETWORK AND DIGITAL PINS ±5 V ADC DRIVER 5 V FULL SYSTEM 5 V FET INPUT AMPLIFIER 5 V INTERNAL SWITCHING NETWORK AND DIGITAL PINS 5 V ADC DRIVER TIMING SPECIFICATIONS Timing Diagrams for Serial Mode ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE MAXIMUM POWER DISSIPATION ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISITICS FULL SYSTEM FET INPUT AMPLIFIER ADC DRIVER TEST CIRCUITS THEORY OF OPERATION KELVIN SWITCHING TECHNIQUES APPLICATIONS INFORMATION CONFIGURING THE ADA4350 SELECTING THE TRANSIMPEDANCE GAIN PATHS MANUALLY OR THROUGH THE PARALLEL INTERFACE SELECTING THE TRANSIMPEDANCE GAIN PATHS THROUGH THE SPI INTERFACE (SERIAL MODE) SPICE MODEL TRANSIMPEDANCE AMPLIFIER DESIGN THEORY TRANSIMPEDANCE GAIN AMPLIFIER PERFORMANCE THE EFFECT OF LOW FEEDBACK RESISTOR RFx USING THE T NETWORK TO IMPLEMENT LARGE FEEDBACK RESISTOR VALUES OUTLINE DIMENSIONS ORDERING GUIDE