Datasheet MLX75027 (Melexis) - 8
| Hersteller | Melexis |
| Beschreibung | VGA Time-of-Flight Sensor |
| Seiten / Seite | 67 / 8 — MLX75027 VGA Time-of-Flight Sensor. 2. Sensor Block Diagram |
| Dateiformat / Größe | PDF / 3.2 Mb |
| Dokumentensprache | Englisch |
MLX75027 VGA Time-of-Flight Sensor. 2. Sensor Block Diagram
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MLX75027 VGA Time-of-Flight Sensor
PRELIMINARY DATASHEET
2. Sensor Block Diagram
MLX75027 is a Time-of-Flight (TOF) camera sensor with two tap Current Assisted Photo Demodulator (CAPD) pixels offering high responsivity. These backside illuminated pixels are connected to low noise analog amplifiers and converted by column ADCs which enable high speed & accurate image acquisition. Furthermore, it consists of a PLL timing generator, a high speed CSI2 serial interface, controllable registers via I2C and a digital control unit in charge of the different internal blocks. VBO1, VRL1, VDDD VBO2 VRSTL VRL2 AGND VDDD 4.7 µF 1 µF 4.7 µF 1 kW SCL 1 kW Biasing External Decoupling I2C SDA POR SLASEL Registers LEDEN Illumination 8 MHz LEDP, LEDN Control Timing Generator (PLL) CLK DGND Phase Delay LEDFB Measurement MIX Drivers Feat ure Currently Not Supported! TRIG GER Digital Control TOF Pixel Array RESETB 640 x 480 Temperature Sensor CSI_CLKx CSI-2 A/D Converter CSI_DATxx Video Interface AGND DGN D Figure 2: Sensor block diagram Preliminary Datasheet v0.9 Page 8 of 67 Document Outline Table of Contents Document Revision History Ordering Information 1. System Architecture 2. Sensor Block Diagram 3. Electrical Specifications 3.1. Absolute Maximum Ratings 3.2. Typical Operating Conditions 3.3. Video Interface 3.3.1. MIPI DC specification 3.3.2. MIPI AC specification 3.4. Power Consumption 3.5. Maximum Distance Frame Rate 3.6. Decoupling Recommendations 3.7. Power-up Sequence 3.8. Input Clock Requirements 3.9. I2C Specifications 4. Optical Characteristics 4.1. VGA Pixel Array Configuration 4.2. Pixel & Image Array Characteristics 4.3. CRA (Chief Ray Angle) 4.4. MTF (Modulation Transfer Function ) 4.5. Application Lens Design Recommendations 5. Communication Interface(s) 5.1. I2C (Inter-Integrated Circuit) 5.1.1. I2C Timing Sequence 5.1.2. Single I2C Read 5.1.3. Sequential I2C Read 5.1.4. Single I2C Write 5.1.5. Sequential I2C Write 5.1.6. I2C Slave Address 5.2. MIPI Alliance CSI-2 Description 5.2.1. Packet Structure 5.2.2. Data Format RAW12 5.2.2.1. Data Format in 4 Lane MIPI Configuration 5.2.2.2. Data Format in 2 Lane MIPI Configuration 6. Start-up Sequence 6.1. Initialization Process 6.2. Initialization Register Map 7. Register Settings 7.1. Video Output Configuration 7.2. Modes of Operation 7.3. Data Output Modes 7.4. HMAX & Frame Read-Out Time 7.4.1. PLLSSETUP 7.4.2. PRETIME 7.4.3. RANDNM0 7.5. PARAM_HOLD 7.6. USER_ID Register 7.7. Modulation Frequency 7.8. Frame Structure & Frame Rate 7.9. FRAME_STARTUP 7.10. FRAME_TIME 7.11. PHASE_COUNT 7.12. Px_PREHEAT, Px_PREMIX 7.13. Px_INTEGRATION 7.14. Px_PHASE_SHIFT 7.15. Px_PHASE_IDLE (or V-blanking) 7.16. Px_LEDEN 7.17. Px_DMIX0, Px_DMIX1 & Px_STATIC_LED 7.18. Analog Delay Setting 7.18.1. Coarse Delay 7.18.2. Fine Delay 7.18.3. Super Fine 7.19. Pixel Binning 7.20. Region of Interest (ROI) 7.21. Flip & Mirror 7.22. Temperature Sensor 7.23. Pixel & Phase Statistics 7.24. PN9 Test Pattern 7.25. Duty Cycle Adjustment 7.26. Illumination Signal (subLVDS or CMOS) 8. MetaData Description 8.1. Embedded Data Format in 4 Lane MIPI Configuration 8.2. Embedded Data Format in 2 Lane MIPI Configuration 9. Distance & Amplitude Calculation 10. Package Information 10.1. Transmittance and Reflectance 10.2. Pinout & Equivalent I/O Circuitry 10.3. Mechanical Dimensions 10.4. Package Marking 10.5. PCB Landing Pattern 10.6. Reflow Solder Profile 10.7. Reflow Cleaning Instructions 10.8. Cover Tape Removal Disclaimer
PRELIMINARY DATASHEET
2. Sensor Block Diagram
MLX75027 is a Time-of-Flight (TOF) camera sensor with two tap Current Assisted Photo Demodulator (CAPD) pixels offering high responsivity. These backside illuminated pixels are connected to low noise analog amplifiers and converted by column ADCs which enable high speed & accurate image acquisition. Furthermore, it consists of a PLL timing generator, a high speed CSI2 serial interface, controllable registers via I2C and a digital control unit in charge of the different internal blocks. VBO1, VRL1, VDDD VBO2 VRSTL VRL2 AGND VDDD 4.7 µF 1 µF 4.7 µF 1 kW SCL 1 kW Biasing External Decoupling I2C SDA POR SLASEL Registers LEDEN Illumination 8 MHz LEDP, LEDN Control Timing Generator (PLL) CLK DGND Phase Delay LEDFB Measurement MIX Drivers Feat ure Currently Not Supported! TRIG GER Digital Control TOF Pixel Array RESETB 640 x 480 Temperature Sensor CSI_CLKx CSI-2 A/D Converter CSI_DATxx Video Interface AGND DGN D Figure 2: Sensor block diagram Preliminary Datasheet v0.9 Page 8 of 67 Document Outline Table of Contents Document Revision History Ordering Information 1. System Architecture 2. Sensor Block Diagram 3. Electrical Specifications 3.1. Absolute Maximum Ratings 3.2. Typical Operating Conditions 3.3. Video Interface 3.3.1. MIPI DC specification 3.3.2. MIPI AC specification 3.4. Power Consumption 3.5. Maximum Distance Frame Rate 3.6. Decoupling Recommendations 3.7. Power-up Sequence 3.8. Input Clock Requirements 3.9. I2C Specifications 4. Optical Characteristics 4.1. VGA Pixel Array Configuration 4.2. Pixel & Image Array Characteristics 4.3. CRA (Chief Ray Angle) 4.4. MTF (Modulation Transfer Function ) 4.5. Application Lens Design Recommendations 5. Communication Interface(s) 5.1. I2C (Inter-Integrated Circuit) 5.1.1. I2C Timing Sequence 5.1.2. Single I2C Read 5.1.3. Sequential I2C Read 5.1.4. Single I2C Write 5.1.5. Sequential I2C Write 5.1.6. I2C Slave Address 5.2. MIPI Alliance CSI-2 Description 5.2.1. Packet Structure 5.2.2. Data Format RAW12 5.2.2.1. Data Format in 4 Lane MIPI Configuration 5.2.2.2. Data Format in 2 Lane MIPI Configuration 6. Start-up Sequence 6.1. Initialization Process 6.2. Initialization Register Map 7. Register Settings 7.1. Video Output Configuration 7.2. Modes of Operation 7.3. Data Output Modes 7.4. HMAX & Frame Read-Out Time 7.4.1. PLLSSETUP 7.4.2. PRETIME 7.4.3. RANDNM0 7.5. PARAM_HOLD 7.6. USER_ID Register 7.7. Modulation Frequency 7.8. Frame Structure & Frame Rate 7.9. FRAME_STARTUP 7.10. FRAME_TIME 7.11. PHASE_COUNT 7.12. Px_PREHEAT, Px_PREMIX 7.13. Px_INTEGRATION 7.14. Px_PHASE_SHIFT 7.15. Px_PHASE_IDLE (or V-blanking) 7.16. Px_LEDEN 7.17. Px_DMIX0, Px_DMIX1 & Px_STATIC_LED 7.18. Analog Delay Setting 7.18.1. Coarse Delay 7.18.2. Fine Delay 7.18.3. Super Fine 7.19. Pixel Binning 7.20. Region of Interest (ROI) 7.21. Flip & Mirror 7.22. Temperature Sensor 7.23. Pixel & Phase Statistics 7.24. PN9 Test Pattern 7.25. Duty Cycle Adjustment 7.26. Illumination Signal (subLVDS or CMOS) 8. MetaData Description 8.1. Embedded Data Format in 4 Lane MIPI Configuration 8.2. Embedded Data Format in 2 Lane MIPI Configuration 9. Distance & Amplitude Calculation 10. Package Information 10.1. Transmittance and Reflectance 10.2. Pinout & Equivalent I/O Circuitry 10.3. Mechanical Dimensions 10.4. Package Marking 10.5. PCB Landing Pattern 10.6. Reflow Solder Profile 10.7. Reflow Cleaning Instructions 10.8. Cover Tape Removal Disclaimer