Datasheet M29W040B (STMicroelectronics) - 8

M29W040B STATUS REGISTER Toggle Bit (DQ6).
The Toggle Bit can be used to Bus Read operations from any address always identify whether the Program/Erase Controller has read the Status Register during Program and successfully completed its operation or if it has re- Erase operations. It is also read during Erase Sus- sponded to an Erase Suspend. The Toggle Bit is pend when an address within a block being erased output on DQ6 when the Status Register is read. is accessed. During Program and Erase operations the Toggle The bits in the Status Register are summarized in Bit changes from ‘0’ to ‘1’ to ‘0’, etc., with succes- Table 7, Status Register Bits. sive Bus Read operations at any address. After successful completion of the operation the memo-
Data Polling Bit (DQ7).
The Data Polling Bit can ry returns to Read mode. be used to identify whether the Program/Erase Controller has successfully completed its opera- During Erase Suspend mode the Toggle Bit will tion or if it has responded to an Erase Suspend. output when addressing a cell within a block being The Data Polling Bit is output on DQ7 when the erased. The Toggle Bit will stop toggling when the Status Register is read. Program/Erase Controller has suspended the Erase operation. During Program operations the Data Polling Bit outputs the complement of the bit being pro- Figure 4, Data Toggle Flowchart, gives an exam- grammed to DQ7. After successful completion of ple of how to use the Data Toggle Bit. the Program operation the memory returns to
Error Bit (DQ5).
The Error Bit can be used to Read mode and Bus Read operations from the ad- identify errors detected by the Program/Erase dress just programmed output DQ7, not its com- Controller. The Error Bit is set to ‘1’ when a Pro- plement. gram, Block Erase or Chip Erase operation fails to During Erase operations the Data Polling Bit out- write the correct data to the memory. If the Error puts ‘0’, the complement of the erased state of Bit is set a Read/Reset command must be issued DQ7. After successful completion of the Erase op- before other commands are issued. The Error bit eration the memory returns to Read mode. is output on DQ5 when the Status Register is read. In Erase Suspend mode the Data Polling Bit will Note that the Program command cannot change a output a ‘1’ during a Bus Read operation within a bit set at ‘0’ back to ‘1’ and attempting to do so may block being erased. The Data Polling Bit will or may not set DQ5 at ‘1’. In both cases, a succes- change from a ‘0’ to a ‘1’ when the Program/Erase sive Bus Read operation will show the bit is still ‘0’. Controller has suspended the Erase operation. One of the Erase commands must be used to set all the bits in a block or in the whole memory from Figure 3, Data Polling Flowchart, gives an exam- ‘0’ to ‘1’. ple of how to use the Data Polling Bit. A Valid Ad- dress is the address being programmed or an address within the block being erased.
Table 7. Status Register Bits Operation Address DQ7 DQ6 DQ5 DQ3 DQ2
Program Any Address DQ7 Toggle 0 – – Program During Erase Any Address DQ7 Toggle 0 – – Suspend Program Error Any Address DQ7 Toggle 1 – – Chip Erase Any Address 0 Toggle 0 1 Toggle Block Erase before Erasing Block 0 Toggle 0 0 Toggle timeout Non-Erasing Block 0 Toggle 0 0 No Toggle Erasing Block 0 Toggle 0 1 Toggle Block Erase Non-Erasing Block 0 Toggle 0 1 No Toggle Erasing Block 1 No Toggle 0 – Toggle Erase Suspend Non-Erasing Block Data read as normal Good Block Address 0 Toggle 1 1 No Toggle Erase Error Faulty Block Address 0 Toggle 1 1 Toggle Note: Unspecified data bits should be ignored. 8/20 Document Outline Table 1. Signal Names Table 2. Absolute Maximum Ratings (1) Table 3. Uniform Block Addresses, M29W040B Table 4. Bus Operations Table 5. Commands Read/Reset. Auto Select. Program, Unlock Bypass Program, Chip Erase, Block Erase. Unlock Bypass. Unlock Bypass Reset. Erase Suspend. Erase Resume. Table 6. Program, Erase Times and Program, Erase Endurance Cycles (TA = 0 to 70˚C or –40 to 85˚C) Table 7. Status Register Bits Table 8. AC Measurement Conditions Table 9. Capacitance (TA = 25 ˚C, f = 1 MHz) Table 10. DC Characteristics (TA = 0 to 70˚C or –40 to 85˚C) Table 11. Read AC Characteristics (TA = 0 to 70˚C or –40 to 85˚C) Table 12. Write AC Characteristics, Write Enable Controlled (TA = 0 to 70˚C or –40 to 85˚C) Table 13. Write AC Characteristics, Chip Enable Controlled (TA = 0 to 70˚C or –40 to 85˚C) Table 14. Ordering Information Scheme Table 15. PLCC32 – 32 lead Plastic Leaded Chip Carrier, Package Mechanical Data Table 16. TSOP32 – 32 lead Plastic Thin Small Outline, 8 x 20mm, Package Mechanical Data Table 17. TSOP32 – 32 lead Plastic Thin Small Outline, 8 x 14mm, Package Mechanical Data Table 18. Revision History SUMMARY DESCRIPTION SIGNAL DESCRIPTIONS Address Inputs (A0-A18). Data Inputs/Outputs (DQ0-DQ7). Chip Enable (E). Output Enable (G). Write Enable (W). VCC Supply Voltage. VSS Ground. BUS OPERATIONS Bus Read. Bus Write. Output Disable. Standby. Automatic Standby. Special Bus Operations Electronic Signature. Block Protection and Blocks Unprotection. COMMAND INTERFACE Read/Reset Command. Auto Select Command. Program Command. Unlock Bypass Command. Unlock Bypass Program Command. Unlock Bypass Reset Command. Chip Erase Command. Block Erase Command. Erase Suspend Command. Erase Resume Command. STATUS REGISTER Data Polling Bit (DQ7). Toggle Bit (DQ6). Error Bit (DQ5). Erase Timer Bit (DQ3). Alternative Toggle Bit (DQ2). Figure 1. Logic Diagram Figure 2. PLCC Connections Figure 3. TSOP Connections Figure 4. Data Polling Flowchart Figure 5. Data Toggle Flowchart Figure 6. AC Testing Input Output Waveform Figure 7. AC Testing Load Circuit Figure 8. Read Mode AC Waveforms Figure 9. Write AC Waveforms, Write Enable Controlled Figure 10. Write AC Waveforms, Chip Enable Controlled Figure 11. PLCC32 – 32 lead Plastic Leaded Chip Carrier, Package Outline Figure 12. TSOP32 – 32 lead Plastic Thin Small Outline, 8 x 20mm, Package Outline Figure 13. TSOP32 – 32 lead Plastic Thin Small Outline, 8 x 14mm, Package Outline