Datasheet AD1835A (Analog Devices) - 4

AD1835A TIMING SPECIFICATIONS Parameter Min Max Unit Comments
MASTER CLOCK AND RESET tMH MCLK High 15 ns tML MCLK Low 15 ns t PD PDR /RST Low 20 ns SPI® PORT tCCH CCLK High 40 ns tCCL CCLK Low 40 ns tCCP CCLK Period 80 ns tCDS CDATA Setup 10 ns To CCLK Rising tCDH CDATA Hold 10 ns From CCLK Rising tCLS CLATCH Setup 10 ns To CCLK Rising tCLH CLATCH Hold 10 ns From CCLK Rising tCOE COUT Enable 15 ns From CLATCH Falling tCOD COUT Delay 20 ns From CCLK Falling tCOTS COUT Three-State 25 ns From CLATCH Rising DAC SERIAL PORT (48 kHz and 96 kHz) Normal Mode (Slave) tDBH DBCLK High 60 ns tDBL DBCLK Low 60 ns fDB DBCLK Frequency 64 ⫻ fS tDLS DLRCLK Setup 10 ns To DBCLK Rising tDLH DLRCLK Hold 10 ns From DBCLK Rising tDDS DSDATA Setup 10 ns To DBCLK Rising tDDH DSDATA Hold 10 ns From DBCLK Rising Packed 128/256 Modes (Slave) tDBH DBCLK High 15 ns tDBL DBCLK Low 15 ns fDB DBCLK Frequency 256 ⫻ fS tDLS DLRCLK Setup 10 ns To DBCLK Rising tDLH DLRCLK Hold 10 ns From DBCLK Rising tDDS DSDATA Setup 10 ns To DBCLK Rising tDDH DSDATA Delay 10 ns From DBCLK Rising ADC SERIAL PORT (48 kHz and 96 kHz) Normal Mode (Master) tABD ABCLK Delay 25 ns From MCLK Rising Edge tALD ALRCLK Delay Low 5 ns From ABCLK Falling Edge tABDD ASDATA Delay 10 ns From ABCLK Falling Edge Normal Mode (Slave) tABH ABCLK High 60 ns tABL ABCLK Low 60 ns fAB ABCLK Frequency 64 ⫻ fS tALS ALRCLK Setup 5 ns To ABCLK Rising tALH ALRCLK Hold 15 ns From ABCLK Rising tABDD ASDATA Delay 15 ns From ABCLK Falling Edge Packed 128/256 Mode (Master) tPABD ABCLK Delay 40 ns From MCLK Rising Edge tPALD LRCLK Delay 5 ns From ABCLK Falling Edge tPABDD ASDATA Delay 10 ns From ABCLK Falling Edge –4– REV. A Document Outline FEATURES APPLICATIONS PRODUCT OVERVIEW FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS TEMPERATURE RANGE ORDERING GUIDE PIN CONFIGURATION PIN FUNCTION DESCRIPTIONS Typical Performance Characteristics DEFINITIONS Dynamic Range Signal-to-(Total Harmonic Distortion + Noise)[S/(THD + N)] Pass Band Pass-Band Ripple Stop Band Gain Error Interchannel Gain Mismatch Gain Drift Crosstalk (EIAJ Method) Power Supply Rejection Group Delay Group Delay Variation GLOSSARY FUNCTIONAL OVERVIEW ADCs DACs DAC and ADC Coding AD1835A CLOCKING SCHEME Selecting DAC Sampling Rate Selecting an ADC Sample Rate RESET and Power-Down Power Supply and Voltage Reference Serial Control Port Serial Data Ports—Data Format Packed Modes Auxiliary (TDM) Mode CONTROL/STATUS REGISTERS DAC Control Registers Sample Rate Power-Down/Reset DAC Data-Word Width DAC Data Format De-emphasis Mute DAC Stereo Replicate DAC Volume Control ADC Control Registers ADC Peak Level Sample Rate ADC Power-Down High-Pass Filter ADC Data-Word Width ADC Data Format Master/Slave Auxiliary Mode ADC Peak Readback CASCADE MODE Dual AD1835A Cascade OUTLINE DIMENSIONS Revision History