Datasheet ADSP-21369 (Analog Devices) - 8

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ADSP-21369 Asynchronous Memory Controller
data or as seven channels plus a single 20-bit wide synchronous parallel data acquisition port. Each data channel has its own The asynchronous memory controller provides a configurable DMA channel that is independent from the processor’s serial interface for up to four separate banks of memory or I/O ports. devices. Each bank can be independently programmed with dif- ferent timing parameters, enabling connection to a wide variety For complete information on using the DAI, see the of memory devices including SRAM, ROM, flash, and EPROM, ADSP-2137x SHARC Processor Hardware Reference. as well as I/O devices that interface with standard memory
Serial Ports
control lines. Bank 0 occupies a 14M word window and Banks 1, 2, and 3 occupy a 16M word window in the processor’s address The processors feature eight synchronous serial ports (SPORTs) space but, if not fully populated, these windows are not made that provide an inexpensive interface to a wide variety of digital contiguous by the memory controller logic. The banks can also and mixed-signal peripheral devices such as Analog Devices’ be configured as 8-bit, 16-bit, or 32-bit wide buses for ease of AD183x family of audio codecs, ADCs, and DACs. The serial interfacing to a range of memories and I/O devices tailored ports are made up of two data lines, a clock, and frame sync. The either to high performance or to low cost and power. data lines can be programmed to either transmit or receive and each data line has a dedicated DMA channel.
Pulse-Width Modulation
Serial ports are enabled via 16 programmable and simultaneous The PWM module is a flexible, programmable, PWM waveform receive or transmit pins that support up to 32 transmit or 32 generator that can be programmed to generate the required receive channels of audio data when all eight SPORTs are switching patterns for various applications related to motor and enabled, or eight full duplex TDM streams of 128 channels engine control or audio power control. The PWM generator can per frame. generate either center-aligned or edge-aligned PWM wave- The serial ports operate at a maximum data rate of 50 Mbps. forms. In addition, it can generate complementary signals on Serial port data can be automatically transferred to and from two outputs in paired mode or independent signals in non- on-chip memory via dedicated DMA channels. Each of the paired mode (applicable to a single group of four PWM serial ports can work in conjunction with another serial port to waveforms). provide TDM support. One SPORT provides two transmit sig- The entire PWM module has four groups of four PWM outputs nals while the other SPORT provides the two receive signals. each. Therefore, this module generates 16 PWM outputs in The frame sync and clock are shared. total. Each PWM group produces two pairs of PWM signals on Serial ports operate in five modes: the four PWM outputs. • Standard DSP serial mode The PWM generator is capable of operating in two distinct modes while generating center-aligned PWM waveforms: single • Multichannel (TDM) mode with support for packed I2S update mode or double update mode. In single update mode, mode the duty cycle values are programmable only once per PWM • I2S mode period. This results in PWM patterns that are symmetrical about the midpoint of the PWM period. In double update • Packed I2S mode mode, a second updating of the PWM registers is implemented • Left-justified sample pair mode at the midpoint of the PWM period. In this mode, it is possible Left-justified sample pair mode is a mode where in each frame to produce asymmetrical PWM patterns that produce lower sync cycle two samples of data are transmitted/received—one harmonic distortion in 2-phase PWM inverters. sample on the high segment of the frame sync, the other on the
Digital Applications Interface (DAI)
low segment of the frame sync. Programs have control over var- ious attributes of this mode. The digital applications interface (DAI) provides the ability to connect various peripherals to any of the DAI pins of the DSP Each of the serial ports supports the left-justified sample pair (DAI_P20–1). Programs make these connections using the sig- and I2S protocols (I2S is an industry-standard interface com- nal routing unit (SRU1), shown in Figure 1. monly used by audio codecs, ADCs, and DACs such as the Analog Devices AD183x family), with two data pins, allowing The SRU is a matrix routing unit (or group of multiplexers) that four left-justified sample pair or I2S channels (using two stereo enables the peripherals provided by the DAI to be intercon- devices) per serial port, with a maximum of up to 32 I2S chan- nected under software control. This allows easy use of the nels. The serial ports permit little-endian or big-endian associated peripherals for a much wider variety of applications transmission formats and word lengths selectable from 3 bits to by using a larger set of algorithms than is possible with noncon- 32 bits. For the left-justified sample pair and I2S modes, data- figurable signal paths. word lengths are selectable between 8 bits and 32 bits. Serial The DAI includes eight serial ports, an S/PDIF receiver/trans- ports offer selectable synchronization and transmit modes as mitter, four precision clock generators (PCG), eight channels of well as optional -law or A-law companding selection on a per synchronous sample rate converters, and an input data port channel basis. Serial port clocks and frame syncs can be inter- (IDP). The IDP provides an additional input path to the nally or externally generated. processor core, configurable as either eight channels of I2S serial Rev. H | Page 8 of 60 | March 2019 Document Outline Summary Dedicated Audio Components Table of Contents Revision History General Description SHARC Family Core Architecture SIMD Computational Engine Independent, Parallel Computation Units Data Register File Context Switch Universal Registers Timer Single-Cycle Fetch of Instruction and Four Operands Instruction Cache Data Address Generators with Zero-Overhead Hardware Circular Buffer Support Flexible Instruction Set On-Chip Memory On-Chip Memory Bandwidth ROM-Based Security Family Peripheral Architecture External Port SDRAM Controller External Memory Shared External Memory External Port Throughput Asynchronous Memory Controller Pulse-Width Modulation Digital Applications Interface (DAI) Serial Ports S/PDIF-Compatible Digital Audio Receiver/Transmitter Synchronous/Asynchronous Sample Rate Converter Input Data Port Precision Clock Generators Digital Peripheral Interface (DPI) Serial Peripheral (Compatible) Interface UART Port Peripheral Timers 2-Wire Interface Port (TWI) I/O Processor Features DMA Controller Delay Line DMA System Design Program Booting Power Supplies Target Board JTAG Emulator Connector Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Pin Function Descriptions Specifications Operating Conditions Electrical Characteristics ESD Caution Maximum Power Dissipation Absolute Maximum Ratings Timing Specifications Core Clock Requirements Voltage Controlled Oscillator Power-Up Sequencing Clock Input Clock Signals Reset Interrupts Core Timer Timer PWM_OUT Cycle Timing Timer WDTH_CAP Timing Pin to Pin Direct Routing (DAI and DPI) Precision Clock Generator (Direct Pin Routing) Flags SDRAM Interface Timing (166 MHz SDCLK) SDRAM Interface Enable/Disable Timing (166 MHz SDCLK) Memory Read Memory Write Asynchronous Memory Interface (AMI) Enable/Disable Shared Memory Bus Request Serial Ports Input Data Port Parallel Data Acquisition Port (PDAP) Pulse-Width Modulation Generators Sample Rate Converter—Serial Input Port Sample Rate Converter—Serial Output Port S/PDIF Transmitter S/PDIF Transmitter—Serial Input Waveforms S/PDIF Transmitter Input Data Timing Oversampling Clock (TxCLK) Switching Characteristics S/PDIF Receiver Internal Digital PLL Mode SPI Interface—Master SPI Interface—Slave JTAG Test Access Port and Emulation Output Drive Currents Test Conditions Capacitive Loading Thermal Characteristics 256-Ball BGA_ED Pinout 208-Lead LQFP_EP Pinout Package Dimensions Surface-Mount Design Ordering Guide