Preliminary Datasheet ADSP-21562, ADSP-21563, ADSP-21565 (Analog Devices) - 7

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Preliminary Technical Data ADSP-21562/21563/21565 Core Timer
32-bit values from memory—all in a single instruction. Addi- tionally, the double-precision floating-point instruction set is an The SHARC+ processor core also has a timer. This extra timer is addition to the SHARC+ core. clocked by the internal processor clock and is typically used as a system tick clock for generating periodic operating system
Variable Instruction Set Architecture (VISA)
interrupts. In addition to supporting the standard 48-bit instructions from
Data Register File
previous SHARC processors, the SHARC+ core processors sup- port 16-bit and 32-bit opcodes for many instructions, formerly Each processing element contains a general-purpose data regis- 48-bit in the ISA. This feature, called variable instruction set ter file. The register files transfer data between the computation architecture (VISA), drops redundant or unused bits within the units and the data buses, and store intermediate results. These 48-bit instruction to create more efficient and compact code. 10-port, 32-register register files (16 primary, 16 secondary), The program sequencer supports fetching these 16-bit and 32- combined with the enhanced Harvard architecture of the pro- bit instructions from both internal and external memories. cessor, allow unconstrained data flow between computation VISA is not an operating mode; it is only address dependent units and internal memory. The registers in the PEx data regis- (refer to memory map ISA/VISA address spaces in Table 5). ter file are referred to as R0–R15 and in the PEy data register file Furthermore, it allows jumps between ISA and VISA instruc- as S0–S15. tion fetches.
Context Switch Single-Cycle Fetch of Instructional Four Operands
Many of the registers of the processor have secondary registers The ADSP-2156x processors feature an enhanced Harvard that can activate during interrupt servicing for a fast context architecture in which the DM bus transfers data and PM bus switch. The data, DAG, and multiplier result registers have sec- transfers both instructions and data. ondary registers. The primary registers are active at reset, while control bits in MODE1 activate the secondary registers. With the separate program memory bus, data memory buses, and on-chip instruction conflict cache, the processor can simul-
Universal Registers
taneously fetch four operands (two over each data bus) and one General-purpose tasks use the universal registers. The four instruction from the conflict cache, in a single cycle. USTAT registers allow easy bit manipulations (set, clear, toggle,
Core Event Controller (CEC)
test, XOR) for all control and status peripheral registers. The SHARC+ core generates various core interrupts (including The data bus exchange register (PX) permits data to pass arithmetic and circular buffer instruction flow exceptions) and between the 64-bit PM data bus and the 64-bit DM data bus or SEC events (debug or monitor and software). The core only between the 40-bit register file and the PM or DM data bus. responds to unmasked interrupts (enabled in the IMASK These registers contain hardware to handle the data width register). difference.
Instruction Conflict Cache Data Address Generators (DAG) With Zero-Overhead Hardware Circular Buffer Support
The processors include a 32-entry instruction cache that enables three-bus operation for fetching an instruction and four data For indirect addressing and implementing circular data buffers values. The cache is selective—only the instructions that require in hardware, the ADSP-2156x processor uses the two data fetches conflict with the PM bus data accesses cache. This cache address generators (DAGs). Circular buffers allow efficient pro- allows full speed execution of core, looped operations, such as gramming of delay lines and other data structures required in digital filter multiply accumulates, and FFT butterfly process- digital signal processing, and are commonly used in digital fil- ing. The conflict cache serves for bus conflicts within the ters and fast Fourier transforms (FFT). The two DAGs of the SHARC+ core only. processors contain sufficient registers to allow the creation of up to 32 circular buffers (16 primary register sets and 16 secondary
Branch Target Buffer (BTB)/Branch Predictor (BP)
sets). The DAGs automatically handle address pointer wrap- Implementation of a hardware-based branch predictor (BP) and around, reduce overhead, increase performance, and simplify branch target buffer (BTB) reduce branch delay. The program implementation. Circular buffers can start and end at any mem- sequencer supports efficient branching using the BTB for condi- ory location. tional and unconditional instructions.
Flexible Instruction Set Architecture (ISA) Addressing Spaces
The flexible instruction set architecture (ISA), a 48-bit instruc- In addition to traditionally supported long word, normal word, tion word, accommodates various parallel operations for extended precision word, and short word addressing aliases, the concise programming. For example, the processors can condi- processors support byte addressing for the data and instruction tionally execute a multiply, an add, and a subtract in both accesses. The enhanced ISA/VISA provides new instructions for processing elements while branching and fetching up to four accessing all sizes of data from byte space as well as converting word addresses to byte and byte to word addresses. Rev. PrG | Page 7 of 95 | June 2020 Document Outline System Features Memory Additional Features Applications Table of Contents Revision History General Description SHARC Processor L1 Memory L1 Master and Slave Ports L1 On-Chip Memory Bandwidth Instruction and Data Cache System Event Controller (SEC) Input Core Memory-Mapped Registers (CMMR) SHARC+ Core Architecture Single-Instruction, Multiple Data (SIMD) Computational Engine Independent Parallel Computation Units Core Timer Data Register File Context Switch Universal Registers Data Address Generators (DAG) With Zero-Overhead Hardware Circular Buffer Support Flexible Instruction Set Architecture (ISA) Variable Instruction Set Architecture (VISA) Single-Cycle Fetch of Instructional Four Operands Core Event Controller (CEC) Instruction Conflict Cache Branch Target Buffer (BTB)/Branch Predictor (BP) Addressing Spaces Additional Features System Infrastructure System L2 Memory One Time Programmable Memory (OTP) I/O Memory Space System Memory Map System Crossbars (SCBs) Direct Memory Access (DMA) Memory Direct Memory Access (MDMA) Extended Memory DMA Cyclic Redundant Code (CRC) Protection Event Handling System Event Controller (SEC) Trigger Routing Unit (TRU) Security Features Cryptographic Hardware Accelerators System Protection Unit (SPU) System Memory Protection Unit (SMPU) Security Features Disclaimer Safety Features Multiparity Bit Protected SHARC+ Core L1 Memories Error Correcting Codes (ECC) Protected L2 Memories Parity-Protected Peripheral Memories Cyclic Redundant Code (CRC) Protected Memories Signal Watchdogs System Event Controller (SEC) Memory Error Controller (MEC) Processor Peripherals Dynamic Memory Controller (DMC) Digital Audio Interface (DAI) Serial Port (SPORT) Asynchronous Sample Rate Converter (ASRC) S/PDIF-Compatible Digital Audio Receiver/Transmitter Precision Clock Generators (PCG) Universal Asynchronous Receiver/Transmitter (UART) Ports Serial Peripheral Interface (SPI) Ports Octal Serial Peripheral Interface (OSPI) Port Link Port (LP) Timers General-Purpose (GP) Timers (TIMER) Watchdog Timer (WDT) General-Purpose Counters (CNT) Media Local Bus (MediaLB) 2-Wire Controller Interface (TWI) General-Purpose I/O (GPIO) Pin Interrupts System Acceleration Finite Impulse Response (FIR) Accelerator Infinite Impulse Response (IIR) Accelerator System Design Clock Management Reset Control Unit (RCU) Clock Generation Unit (CGU) System Crystal Oscillator Clock Distribution Unit (CDU) Clock Out/External Clock Booting Power Supplies Power Management Power-Up and Power-Down Sequencing Target Board JTAG Emulator Connector System Debug System Watchpoint Unit (SWU) Debug Access Port (DAP) Development Tools Integrated Development Environments (IDEs) EZ-KIT Evaluation Board EZ-KIT Evaluation Kits Software Add Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains ADSP-2156x Detailed Signal Descriptions 400-Ball CSP_BGA Signal Descriptions GPIO Multiplexing for 400-Ball CSP_BGA Package 120-Lead LQFP Signal Descriptions GPIO Multiplexing for 120-Lead LQFP ADSP-2156x Designer Quick Reference Preliminary Specifications Preliminary Operating Conditions Preliminary Clock Related Operating Conditions Preliminary Electrical Characteristics Absolute Maximum Ratings ESD Caution Timing Specifications Power-Up Reset Timing Clock and Reset Timing Link Ports (LPs) Serial Ports (SPORTs) Asynchronous Sample Rate Converter (ASRC)—Serial Input Port Asynchronous Sample Rate Converter (ASRC)—Serial Output Port SPI Port—Master Timing SPI0, SPI1, and SPI2 SPI Port—Slave Timing SPI0, SPI1, and SPI2 SPI Port—SPIx_RDY Slave Timing SPI Port—Open Drain Mode (ODM) Timing SPI Port—SPIx_RDY Master Timing OSPI Port—Master Timing OSPI0 Precision Clock Generator (PCG) (Direct Pin Routing) General-Purpose IO Port Timing General-Purpose I/O Timer Cycle Timing DAIx Pin to DAIx Pin Direct Routing (DAI0 Block and DAI1 Block) Up/Down Counter/Rotary Encoder Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing Sony/Philips Digital Interface (S/PDIF) Transmitter S/PDIF Transmitter Serial Input Waveforms S/PDIF Transmitter Input Data Timing Oversampling Clock (TxCLK) Switching Characteristics S/PDIF Receiver Internal Digital PLL Mode MediaLB (MLB) Program Trace Macrocell (PTM) Timing Debug Interface (JTAG Emulation Port) Timing ADSP-2156x 400-Ball BGA Ball Assignments ADSP-2156x 400-Ball BGA Ball Assignments (Numerical by Ball Number) ADSP-2156x 400-Ball BGA Ball Assignments (Alphabetical by Pin Name) Configuration of the 400-Ball CSP_BGA ADSP-2156x 120-Lead LQFP Lead Assignments ADSP-2156x 120-Lead LQFP Lead Assignments (Numerical by Lead Number) ADSP-2156x 120-Lead LQFP Lead Assignments (Alphabetical by Pin Name) Configuration of the 120-Lead LQFP Lead Configuration Outline Dimensions Surface-Mount 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