Datasheet ADSP-21566, ADSP-21567, ADSP-21569 (Analog Devices) - 9

ADSP-21566/21567/21569 Table 3. L2 Memory Addressing Map Byte Address Space Normal Word Address Space VISA Address Space ISA Address Space SHARC+ Memory1 SHARC+ Data Access SHARC+ Data Address SHARC+ Instruction Fetch Instruction Fetch
SHARC/DMA: 0x08040000– 0x00B20000– 0x00580000– L2 Boot ROM0 0x20100000–0x20107FFF 0x08041FFF 0x00B23FFF 0x00581555 L2 Boot ROM1 0x20108000– 0x08042000– 0x00B00000– 0x00500000– 0x2010FFFF 0x08043FFF 0x00B03FFF 0x00501555 L2 Boot ROM2 0x20110000– 0x08044000– 0x00B40000– 0x00540000– 0x20117FFF 0x08045FFF 0x00B43FFF 0x00541555 1 The L2 RAM blocks are subdivided into banks—the 8 Mb L2 models have eight banks, the 4 Mb models have four banks, and there are two banks for the 2 Mb models.
Table 4. SHARC+® L1 Memory Space Memory Block Byte Address Space SHARC+ Normal Word Address Space SHARC+
L1 Memory Space Address via Slave1/Slave2 Port Block 0 0x28240000–0x2826FFFF 0x0A090000–0x0A09BFFF Block 1 0x282C0000–0x282EFFFF 0x0A0B0000–0x0A0BBFFF Block 2 0x28300000–0x2831FFFF 0x0A0C0000–0x0A0C7FFF Block 3 0x28380000–0x2839FFFF 0x0A0E0000–0x0A0E7FFF
Table 5. Memory Map of Mapped I/Os1 Byte Address Space Normal Word Address Space VISA Address Space ISA Address Space SHARC+ Data Access SHARC+ Data Access SHARC+ Instruction Fetch SHARC+ Instruction Fetch
SPI2/OSPI0 0x60000000–0x600FFFFF 0x00F80000–0x00FFFFFF 0x00780000–0x007FFFFF Memory 0x60100000–0x602FFFFF 0x04000000–0x07FFFFFF Not applicable (512 MB) 0x60300000–0x6FFFFFFF Not applicable Not applicable 0x70000000–0x7FFFFFFF Not applicable Not applicable Not applicable 1 The SHARC+ VISA/ISA address space for instruction fetch and the normal word address space for data access do not cover the entire byte address space.
Table 6. DMC Memory Map1 Byte Address Space Normal Word Address Space VISA Address Space ISA Address Space SHARC+ Data Access SHARC+ Data Access SHARC+ Instruction Fetch SHARC+ Instruction Fetch
DMC0 (1 GB) 0x80000000–0x805FFFFF Not applicable 0x00400000–0x004FFFFF 0x80600000–0x809FFFFF Not applicable Not applicable 0x10000000–0x17FFFFFF 0x80A00000–0x80FFFFFF 0x00800000–0x00AFFFFF Not applicable 0x81000000–0x9FFFFFFF Not applicable Not applicable 0xA0000000–0xBFFFFFFF Not applicable Not applicable Not applicable 1 The SHARC+ VISA/ISA address space for instruction fetch and the normal word address space for data access do not cover the entire byte address space. Rev. 0 | Page 9 of 98 | March 2020 Document Outline System Features Memory Additional Features Applications Table of Contents Revision History General Description SHARC Processor L1 Memory L1 Master and Slave Ports L1 On-Chip Memory Bandwidth Instruction and Data Cache Core Memory-Mapped Registers (CMMR) SHARC+ Core Architecture Single-Instruction, Multiple Data (SIMD) Computational Engine Independent Parallel Computation Units Core Timer Data Register File Context Switch Universal Registers Data Address Generators (DAG) With Zero Overhead Hardware Circular Buffer Support Flexible Instruction Set Architecture (ISA) Variable Instruction Set Architecture (VISA) Single-Cycle Fetch of Instructional Four Operands Core Event Controller (CEC) Instruction Conflict Cache Branch Target Buffer (BTB)/Branch Predictor (BP) Addressing Spaces Additional Features System Infrastructure System L2 Memory One Time Programmable Memory (OTP) I/O Memory Space System Memory Map System Crossbars (SCBs) Direct Memory Access (DMA) Memory Direct Memory Access (MDMA) Extended Memory DMA Cyclic Redundant Code (CRC) Protection Event Handling System Event Controller (SEC) Trigger Routing Unit (TRU) Security Features Cryptographic Hardware Accelerators System Protection Unit (SPU) System Memory Protection Unit (SMPU) Security Features Disclaimer Safety Features Multiparity Bit Protected SHARC+ Core L1 Memories Error Correcting Code (ECC) Protected L2 Memories Parity Protected Peripheral Memories Cyclic Redundant Code (CRC) Protected Memories Signal Watchdogs System Event Controller (SEC) Memory Error Controller (MEC) Processor Peripherals Dynamic Memory Controller (DMC) Digital Audio Interface (DAI) Serial Port (SPORT) Asynchronous Sample Rate Converter (ASRC) S/PDIF-Compatible Digital Audio Receiver/Transmitter Precision Clock Generators (PCG) Universal Asynchronous Receiver/Transmitter (UART) Ports Serial Peripheral Interface (SPI) Ports Octal Serial Peripheral Interface (OSPI) Port Link Port (LP) Timers General-Purpose (GP) Timers (TIMER) Watchdog Timer (WDT) General-Purpose Counters (CNT) Media Local Bus (MediaLB) 2-Wire Controller Interface (TWI) General-Purpose I/O (GPIO) Pin Interrupts System Acceleration Finite Impulse Response (FIR) Accelerator Infinite Impulse Response (IIR) Accelerator System Design Clock Management Reset Control Unit (RCU) Clock Generation Unit (CGU) System Crystal Oscillator Clock Distribution Unit (CDU) Clock Out/External Clock Booting Power Supplies Power Management Power-Up and Power-Down Sequencing Target Board JTAG Emulator Connector System Debug System Watchpoint Unit (SWU) Debug Access Port (DAP) Development Tools Integrated Development Environments (IDEs) EZ-KIT Evaluation Board EZ-KIT Evaluation Kits Software Add Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains ADSP-2156x Detailed Signal Descriptions 400-Ball CSP_BGA Signal Descriptions GPIO Multiplexing for 400-Ball CSP_BGA Package 120-Lead LQFP Signal Descriptions GPIO Multiplexing for 120-Lead LQFP ADSP-2156x Designer Quick Reference Specifications Operating Conditions Clock Related Operating Conditions Electrical Characteristics Total Internal Power Dissipation Application Dependent Current Clock Current Data Transmission Current Absolute Maximum Ratings ESD Caution Timing Specifications Power-Up Reset Timing Clock and Reset Timing Link Ports (LPs) Serial Ports (SPORTs) Asynchronous Sample Rate Converter (ASRC)—Serial Input Port Asynchronous Sample Rate Converter (ASRC)—Serial Output Port SPI Port—Master Timing SPI0, SPI1, and SPI2 SPI Port—Slave Timing SPI0, SPI1, and SPI2 SPI Port—SPIx_RDY Slave Timing SPI Port—Open Drain Mode (ODM) Timing SPI Port—SPIx_RDY Master Timing OSPI Port—Master Timing OSPI0 Precision Clock Generator (PCG) (Direct Pin Routing) General-Purpose IO Port Timing General-Purpose I/O Timer Cycle Timing DAIx Pin to DAIx Pin Direct Routing (DAI0 Block and DAI1 Block) Up/Down Counter/Rotary Encoder Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing Sony/Philips Digital Interface (S/PDIF) Transmitter S/PDIF Transmitter Serial Input Waveforms S/PDIF Transmitter Input Data Timing Oversampling Clock (TxCLK) Switching Characteristics S/PDIF Receiver Internal Digital PLL Mode MediaLB (MLB) Program Trace Macrocell (PTM) Timing Debug Interface (JTAG Emulation Port) Timing Output Drive Currents Test Conditions Output Enable Time Measurement Output Disable Time Measurement Capacitive Loading Environmental Conditions ADSP-2156x 400-Ball BGA Ball Assignments ADSP-2156x 400-Ball BGA Ball Assignments (Numerical by Ball Number) ADSP-2156x 400-Ball BGA Ball Assignments (Alphabetical by Pin Name) Configuration of the 400-Ball CSP_BGA ADSP-2156x 120-Lead LQFP Lead Assignments ADSP-2156x 120-Lead LQFP Lead Assignments (Numerical by Lead Number) ADSP-2156x 120-Lead LQFP Lead Assignments (Alphabetical by Pin Name) Configuration of the 120-Lead LQFP Lead Configuration Outline Dimensions Surface-Mount Design Planned Automotive Production Products Planned Production Products Ordering Guide