Datasheet ADSP-21566, ADSP-21567, ADSP-21569 (Analog Devices) - 5

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ADSP-21566/21567/21569
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DEBUG FLAGS CEC BTB CONFLICT SIMD Core TRACE BP CACHE PM DATA 48 DMD/PMD 64 11-STAGE PROGRAM SEQUENCER PM ADDRESS 24 DAG1 DAG2 16 × 32 16 × 32 PM ADDRESS 32 SYSTEM DM ADDRESS 32 I/F TO PM DATA 64 IMIF USTAT PX DM DATA 64 PEx DATA PEy SWAP MULTIPLIER SHIFTER ALU DATA DATA ALU SHIFTER MULTIPLIER REGISTER REGISTER Rx Sx 16 × 40-BIT 16 × 40-BIT ASTATx ASTATy MRF MRB MSB MSF 80-BIT 80-BIT 80-BIT 80-BIT STYKx STYKy
Figure 3. SHARC+ SIMD Core Block Diagram cache, with the remaining L1 memory configured as SRAM.
L1 On-Chip Memory Bandwidth
Each addressable memory space outside the L1 memory can be The internal memory architecture allows programs to have four accessed either directly or via cache. accesses at the same time to any of the four blocks, assuming no The memory map in Table 2 gives the L1 memory address space block conflicts. The total bandwidth is realized using both the and shows multiple L1 memory blocks offering a configurable DMD and PMD buses (2 × 64-bits CCLK speed and 2 × 32-bit mix of SRAM and cache. SYSCLK speed).
L1 Master and Slave Ports Instruction and Data Cache
The SHARC+ core has two master/slave ports to and from the The ADSP-2156x processors also include a traditional instruc- system fabric. One master port fetches instructions. The second tion cache (I-cache) and two data caches (D-caches, one each master port drives data to the system world. Slave Port 1 for PM/DM) with parity support for all caches. These caches together with Slave Port 2 memory direct memory access support one instruction access and two data accesses over the (MDMA) run conflict free access to the individual memory DM and PM buses per CCLK cycle. The cache controllers auto- blocks. For the slave port addresses, refer to the L1 memory matically manage the configured L1 memory. The system can address map in Table 2. configure part of the L1 memory for automatic management by the cache controllers. The sizes of these caches are inde- pendently configurable from 0 to 128 kB each. The memory not managed by the cache controllers is directly addressable by the processors. The controllers ensure the data coherence between Rev. 0 | Page 5 of 98 | March 2020 Document Outline System Features Memory Additional Features Applications Table of Contents Revision History General Description SHARC Processor L1 Memory L1 Master and Slave Ports L1 On-Chip Memory Bandwidth Instruction and Data Cache Core Memory-Mapped Registers (CMMR) SHARC+ Core Architecture Single-Instruction, Multiple Data (SIMD) Computational Engine Independent Parallel Computation Units Core Timer Data Register File Context Switch Universal Registers Data Address Generators (DAG) With Zero Overhead Hardware Circular Buffer Support Flexible Instruction Set Architecture (ISA) Variable Instruction Set Architecture (VISA) Single-Cycle Fetch of Instructional Four Operands Core Event Controller (CEC) Instruction Conflict Cache Branch Target Buffer (BTB)/Branch Predictor (BP) Addressing Spaces Additional Features System Infrastructure System L2 Memory One Time Programmable Memory (OTP) I/O Memory Space System Memory Map System Crossbars (SCBs) Direct Memory Access (DMA) Memory Direct Memory Access (MDMA) Extended Memory DMA Cyclic Redundant Code (CRC) Protection Event Handling System Event Controller (SEC) Trigger Routing Unit (TRU) Security Features Cryptographic Hardware Accelerators System Protection Unit (SPU) System Memory Protection Unit (SMPU) Security Features Disclaimer Safety Features Multiparity Bit Protected SHARC+ Core L1 Memories Error Correcting Code (ECC) Protected L2 Memories Parity Protected Peripheral Memories Cyclic Redundant Code (CRC) Protected Memories Signal Watchdogs System Event Controller (SEC) Memory Error Controller (MEC) Processor Peripherals Dynamic Memory Controller (DMC) Digital Audio Interface (DAI) Serial Port (SPORT) Asynchronous Sample Rate Converter (ASRC) S/PDIF-Compatible Digital Audio Receiver/Transmitter Precision Clock Generators (PCG) Universal Asynchronous Receiver/Transmitter (UART) Ports Serial Peripheral Interface (SPI) Ports Octal Serial Peripheral Interface (OSPI) Port Link Port (LP) Timers General-Purpose (GP) Timers (TIMER) Watchdog Timer (WDT) General-Purpose Counters (CNT) Media Local Bus (MediaLB) 2-Wire Controller Interface (TWI) General-Purpose I/O (GPIO) Pin Interrupts System Acceleration Finite Impulse Response (FIR) Accelerator Infinite Impulse Response (IIR) Accelerator System Design Clock Management Reset Control Unit (RCU) Clock Generation Unit (CGU) System Crystal Oscillator Clock Distribution Unit (CDU) Clock Out/External Clock Booting Power Supplies Power Management Power-Up and Power-Down Sequencing Target Board JTAG Emulator Connector System Debug System Watchpoint Unit (SWU) Debug Access Port (DAP) Development Tools Integrated Development Environments (IDEs) EZ-KIT Evaluation Board EZ-KIT Evaluation Kits Software Add Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains ADSP-2156x Detailed Signal Descriptions 400-Ball CSP_BGA Signal Descriptions GPIO Multiplexing for 400-Ball CSP_BGA Package 120-Lead LQFP Signal Descriptions GPIO Multiplexing for 120-Lead LQFP ADSP-2156x Designer Quick Reference Specifications Operating Conditions Clock Related Operating Conditions Electrical Characteristics Total Internal Power Dissipation Application Dependent Current Clock Current Data Transmission Current Absolute Maximum Ratings ESD Caution Timing Specifications Power-Up Reset Timing Clock and Reset Timing Link Ports (LPs) Serial Ports (SPORTs) Asynchronous Sample Rate Converter (ASRC)—Serial Input Port Asynchronous Sample Rate Converter (ASRC)—Serial Output Port SPI Port—Master Timing SPI0, SPI1, and SPI2 SPI Port—Slave Timing SPI0, SPI1, and SPI2 SPI Port—SPIx_RDY Slave Timing SPI Port—Open Drain Mode (ODM) Timing SPI Port—SPIx_RDY Master Timing OSPI Port—Master Timing OSPI0 Precision Clock Generator (PCG) (Direct Pin Routing) General-Purpose IO Port Timing General-Purpose I/O Timer Cycle Timing DAIx Pin to DAIx Pin Direct Routing (DAI0 Block and DAI1 Block) Up/Down Counter/Rotary Encoder Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing Sony/Philips Digital Interface (S/PDIF) Transmitter S/PDIF Transmitter Serial Input Waveforms S/PDIF Transmitter Input Data Timing Oversampling Clock (TxCLK) Switching Characteristics S/PDIF Receiver Internal Digital PLL Mode MediaLB (MLB) Program Trace Macrocell (PTM) Timing Debug Interface (JTAG Emulation Port) Timing Output Drive Currents Test Conditions Output Enable Time Measurement Output Disable Time Measurement Capacitive Loading Environmental Conditions ADSP-2156x 400-Ball BGA Ball Assignments ADSP-2156x 400-Ball BGA Ball Assignments (Numerical by Ball Number) ADSP-2156x 400-Ball BGA Ball Assignments (Alphabetical by Pin Name) Configuration of the 400-Ball CSP_BGA ADSP-2156x 120-Lead LQFP Lead Assignments ADSP-2156x 120-Lead LQFP Lead Assignments (Numerical by Lead Number) ADSP-2156x 120-Lead LQFP Lead Assignments (Alphabetical by Pin Name) Configuration of the 120-Lead LQFP Lead Configuration Outline Dimensions Surface-Mount Design Planned Automotive Production Products Planned Production Products Ordering Guide