Datasheet PE43610 (pSemi) - 10

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PE43610 UltraCMOS® RF Digital Step Attenuator Figure 4 • Latched-Paral el/Direct-Paral el Timing Diagram
D[1] X X D[2] X X D[3] X X D[4] X X D[5] X X D[6] X X T P/S T DIH DISU LE TLEPW Notes: 1. D1 is shared with serial interface data input SDI 2. D2 is shared with serial interface clock input CLK 3. D3 is shared with serial interface data output SDO 4. D4 is shared with serial address bit A0 5. D5 is shared with serial address bit A1 6. D6 is shared with serial address bit A2 7. X = Undefined
Table 10 • Paral el and Direct Interface AC Characteristics (*) Parameter/Condition Min Max Unit
Latch enable minimum pulse width, TLEPW 30 ns Paral el data setup time, TDISU 100 ns Paral el data hold time, TDIH 100 ns
Note: *
VDD = 3.3V or 5.5V, –40 °C < TA < +105 °C, unless otherwise specified. Page 10 of 21 DOC-93588-3 – (06/2020) www.psemi.com Document Outline Features Applications Product Description Optional External VSS Control Absolute Maximum Ratings ESD Precautions Latch-up Immunity Recommended Operating Conditions Electrical Specifications Switching Frequency Spur-free Performance Glitch-safe Attenuation State The PE43610 features a novel architecture to provide safe transition behavior when changing attenuation states. When RF input power is applied, positive output power spikes are prevented during attenuation state changes by optimized internal timing c... Truth Tables Serial Addressable Register Map Programming Options Parallel/Serial Selection Parallel Mode Interface For direct parallel programming, the LE line should be pulled HIGH. Changing attenuation state control values changes the device state to new attenuation. Direct mode is ideal for manual control of the device (using hardwire, switches, or jumpers). Serial-Addressable Interface Power-up Control Settings Typical Performance Data Pin Configuration Packaging Information Moisture Sensitivity Level Package Drawing Top-Marking Specification Tape and Reel Specification Ordering Information