Datasheet PE43610 (pSemi) - 7

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PE43610 UltraCMOS® RF Digital Step Attenuator Programming Options Paral el/Serial Selection
entered into the shift register. Serial data is clocked in Either a paral el or serial addressable interface can be LSB first. The serial interface data output, SDO, used to control the PE43610. The P/S bit provides this outputs serial input data delayed by 16 clock cycles to selection, with P/S = LOW selecting the paral el control the cascaded attenuator using a single serial interface and P/S = HIGH selecting the serial peripheral interface (SPI) bus. interface. The P/S pin has an internal tie HIGH The shift register must be loaded while LE is held (namely, the pin is internal y tied to the 1.8V VDD), so if LOW to prevent the attenuator value from changing this is left floating, the part defaults to serial mode. If as data is entered. The LE input should then be there is a need to put this part in paral el mode, a toggled HIGH and brought LOW again, latching the LOW logic should be applied to this pin. new data into the DSA. The Address Word truth table is listed in
Table 5
. The address pins A0 (pin 22), A1
Paral el Mode Interface
(pin 23), and A2 (pin 24) can either be grounded logic LOW or left floating (logic HIGH due to internal pul -up The paral el interface consists of six CMOS- to 1.8V V compatible control lines that select the desired attenu- DD) depending upon what fixed address the ation state, as shown in
Table 4
. user wants the DSA to be set at.The Attenuation Word truth table is listed in
Table 6
. A programming The paral el interface timing requirements are defined example of the serial register is il ustrated in
Figure 2
. by
Figure 4
(Latched-Paral el/Direct-Paral el Timing The serial timing diagram is il ustrated in
Figure 3
. Diagram),
Table 10
(Paral el and Direct Interface AC Characteristics) and switching time (
Table 3
).
Power-up Control Settings
For latched paral el programming, the latch enable The PE43610 always initializes to the maximum atten- (LE) should be held LOW while changing attenuation uation setting (31.5 dB) on power-up for both the state control values then pulse LE HIGH to LOW (per serial addressable and latched paral el modes of
Figure 4
) to latch new attenuation state into the operation (as long as the LE pin is logic LOW during device. start up) and it remains in this setting until the user latches in the next programming word. For direct paral el programming, the LE line should be pul ed HIGH. Changing attenuation state control val-
In direct parallel mode
(P/S = LOW and logic HIGH ues changes the device state to new attenuation. present on the LE pin during the power-up), the DSA Direct mode is ideal for manual control of the device can be preset to any state within the 31.5 dB range by (using hardwire, switches, or jumpers). pre-setting the paral el control pins D[6:1] prior to power-up. In this mode, there is a 4 µs delay between
Serial-Addressable Interface
the time the DSA is powered-up to the time the The serial-addressable interface is a 16-bit serial-in, desired state is set. If the control pins are left floating paral el-out shift register buffered by a transparent in this mode during power-up, the device defaults to latch. The 16-bits make up two words comprised of 8- the 28dB attenuation setting. bits each. The first word is the attenuation word,
In latched parallel mode
(P/S = LOW), if the LE pin which controls the state of the DSA. The second word is kept LOW during power-up, the part should default is the address word, which is compared to the static to maximum attenuation state (31.5dB). Logic LOW (or programmed) logical states of the A0, A1 and A2 should be present on the LE pin during power-up and digital inputs. If there is an address match, the DSA then logic HIGH should be written on the LE pin when changes state; otherwise its current state remains the user wants to program the part. If the LE is kept unchanged.
Figure 3
il ustrates an example timing floating during power-up, the part should default to diagram for programming a state. maximum attenuation state (31.5dB). The serial-addressable interface is control ed using
In serial mode
(P/S = HIGH or left floating) logic three CMOS-compatible signals: SDI, CLK, and LE. HIGH on the LE pin during the power up: The part The SDI and CLK inputs al ow data to be serial y should default to minimum attenuation state DOC-93588-3 – (06/2020) Page 7 of 21 www.psemi.com Document Outline Features Applications Product Description Optional External VSS Control Absolute Maximum Ratings ESD Precautions Latch-up Immunity Recommended Operating Conditions Electrical Specifications Switching Frequency Spur-free Performance Glitch-safe Attenuation State The PE43610 features a novel architecture to provide safe transition behavior when changing attenuation states. When RF input power is applied, positive output power spikes are prevented during attenuation state changes by optimized internal timing c... Truth Tables Serial Addressable Register Map Programming Options Parallel/Serial Selection Parallel Mode Interface For direct parallel programming, the LE line should be pulled HIGH. Changing attenuation state control values changes the device state to new attenuation. Direct mode is ideal for manual control of the device (using hardwire, switches, or jumpers). Serial-Addressable Interface Power-up Control Settings Typical Performance Data Pin Configuration Packaging Information Moisture Sensitivity Level Package Drawing Top-Marking Specification Tape and Reel Specification Ordering Information