Datasheet AD538 (Analog Devices) - 6

AD538 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS IZ 1 18 A VZ 2 17 D B 3 16 IX +10V AD538 4 15 VX TOP VIEW +2V 5 14 SIGNAL GND (Not to Scale) +VS 6 13 PWR GND –VS 7 12 C VO 8 11 IY
002
I 9 10 VY
00959- Figure 2. Pin Configuration
Table 3. Pin No. Mnemonic Description
1 I Current Input for the Z Multiplicand. Z 2 V Voltage Input for the Z Multiplicand. Z 3 B Output of the Log Ratio Differential Amplifier. This amplifier subtracts the log of the Z input from the log of the X input, or performs the equivalent logarithmic equivalent of long division. 4 +10V +10 V Reference Voltage Output. 5 +2V +2 V Reference Voltage Output. 6 +V Positive Supply Rail. S 7 –V Negative Rail. S 8 V Output Voltage. O 9 I Current Input to the Output Amplifier. 10 V Voltage Input to the Y Multiplicand. Y 11 I Current Input to the Y Multiplicand. Y 12 C Current Input to the Base of the Antilog Log-to-Linear Converter. 13 PWR GND High level Power Return of the Chip. 14 SIGNAL GND Low Level Ground Return of the Device. 15 V Voltage Input of the X Multiplicand. X 16 I Current Input of the X Input Multiplicand. X 17 D Use for Log Ratio Function. 18 A Use for Log Ratio Function. Rev. E | Page 6 of 16 Document Outline Features Applications Functional Block Diagram General Description Revision History Specifications Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Re-Examination of Multiplier/Divider Accuracy Functional Description Stability Precautions Using The Voltage References One-Quadrant Multiplication/Division Two-Quadrant Division Log Ratio Operation Analog Computation Of Powers And Roots Square Root Operation Applications Information Transducer Linearization ARC-Tangent Approximation Outline Dimensions Ordering Guide