Datasheet DA14531 (Dialog Semiconductor) - 9

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DA14531 Ultra Low Power Bluetooth 5.1 SoC Final
33.4 Package Outlines .. 370
Revision History .. 373 Figures
Figure 1: System Diagram ... 2 Figure 2: DA14531 Block Diagram .. 19 Figure 3: WLCSP17 Ball Assignment (Top View) ... 20 Figure 4: FCGQFN24 Pin Assignment (Top View) ... 24 Figure 5: Boost configuration system diagram .. 29 Figure 6: Buck configuration system diagram ... 29 Figure 7: Power Management Unit: Buck Configuration ... 48 Figure 8: Power Management Unit: Boost Configuration .. 48 Figure 9: Power Management Unit: Bypass Configuration ... 49 Figure 10: Digital Power Domains ... 49 Figure 11: Power-Up/Wake-Up/Sleep FSM Diagram .. 56 Figure 12: Power-up (Buck)... 57 Figure 13: Wake-Up from hibernation (Buck) .. 57 Figure 14: Wake-Up (Buck) ... 58 Figure 15: Power-Up (Boost) ... 58 Figure 16: Wake-Up from hibernation (Boost)... 59 Figure 17: Wake-Up from extended/deep sleep (Boost) ... 59 Figure 18: Go-to-Sleep and Bandgap Refresh .. 59 Figure 19: OTP Layout Scheme .. 60 Figure 20: BootROM Sequence .. 65 Figure 21: Reset Block Diagram ... 67 Figure 22: POR Timing Diagram ... 70 Figure 23: Arm Cortex-M0+ Block Diagram .. 71 Figure 24: AMBA Bus Architecture and Power Domains .. 75 Figure 25: Memory Controller Block Diagram ... 79 Figure 26: Clock Tree Diagram ... 81 Figure 27: Crystal Oscillator Circuits ... 83 Figure 28: XTAL32MHz Oscillator Frequency Trimming ... 84 Figure 29: Automated Mechanism for XTAL32M Trim and Settling .. 85 Figure 30: OTP Controller Block Diagram ... 87 Figure 31: DMA Controller Block Diagram .. 90 Figure 32: DMA Channel Diagram .. 92 Figure 33: I2C Controller Block Diagram ... 95 Figure 34: Master/Slave and Transmitter/Receiver Relationships .. 96 Figure 35: Data Transfer on the I2C Bus .. 97 Figure 36: START and STOP Conditions .. 98 Figure 37: 7-bit Address Format .. 99 Figure 38: 10-bit Address Format .. 99 Figure 39: Master-Transmitter Protocol ... 100 Figure 40: Master-Receiver Protocol ... 101 Figure 41: START BYTE Transfer ... 101 Figure 42: Multiple Master Arbitration ... 102 Figure 43: Multiple Master Clock Synchronization .. 103 Figure 44: UART Block Diagram ... 105 Figure 45: Serial Data Format ... 106 Figure 46: Receiver Serial Data Sampling Points ... 106 Figure 47: Flowchart of Interrupt Generation for Programmable THRE Interrupt Mode ... 109 Figure 48: Flowchart of Interrupt Generation When Not in Programmable THRE Interrupt Mode ... 110 Figure 49: SPI Block Diagram ... 112 Figure 50: SPI Slave Mode Timing (CPOL = 0, CPHA = 0) .. 113 Figure 51: Quadrature Decoder Block Diagram .. 116 Figure 52: Moving Forward on Axis X ... 117
Datasheet Revision 3.1 09-Jul-2020
CFR0011-120-00 9 of 374 © 2020 Dialog Semiconductor Document Outline General Description Key Features Applications Key Benefits System Diagram Contents Figures Tables 1 Block Diagram 2 Packages and Pinout 2.1 WLCSP17 2.2 FCGQFN24 3 Specifications 3.1 Absolute Maximum Ratings 3.2 Recommended Operating Conditions 3.3 DC Characteristics 3.4 Timing Characteristics 3.5 RCX Oscillator 3.6 XTAL32MHz Oscillator 3.7 XTAL32kHz Oscillator 3.8 RC32MHz Oscillator 3.9 DC-DC Converter 3.10 LDO_LOW Characteristics 3.11 Digital I/O Characteristics 3.12 Power On Reset 3.13 GP ADC 3.14 Temperature Sensor 3.15 Radio 4 System Overview 4.1 Internal Blocks 4.2 Power Management Unit 4.2.1 Introduction 4.2.2 Architecture 4.2.2.1 Digital Power Domains 4.2.2.2 Power Modes 4.2.2.3 VDD Level in Hibernation 4.2.2.4 Retainable Registers 4.2.3 Programming 4.2.3.1 Buck Configuration 4.2.3.2 Boost Configuration 4.2.3.3 Bypass Configuration 4.3 HW FSM (Power-up, Wake-up, and Go-to-Sleep) 4.3.1 Power-up/Wake-up in Buck Configuration 4.3.2 Power-up/Wake-up in Boost Configuration 4.3.3 Go-to-Sleep and Refresh Bandgap 4.4 OTP Memory Layout 4.4.1 OTP Header 4.4.2 Configuration Script 4.5 BootROM Sequence 5 Reset 5.1 Introduction 5.2 Architecture 5.2.1 POR, HW, and SW Reset 5.2.2 POR Functionality 5.2.2.1 POR Timer Clock 5.2.2.2 RST Pad 5.2.2.3 POR from GPIO 5.2.3 POR Timing Diagram 5.2.4 POR Considerations 5.3 Programming 6 Arm Cortex-M0+ 6.1 Introduction 6.2 Architecture 6.2.1 Interrupts 6.2.2 System Timer (systick) 6.2.3 Wake-Up Interrupt Controller 6.3 Programming 7 AMBA Bus 7.1 Introduction 7.2 Architecture 7.3 Programming 8 Memory Map 9 Memory Controller 9.1 Introduction 9.2 Architecture 9.2.1 Arbitration 10 Clock Generation 10.1 Clock Tree 10.1.1 General Clock Constraints 10.2 Crystal Oscillators 10.2.1 Frequency Control (32 MHz Crystal) 10.2.2 Automated Trimming and Settling Notification 10.3 RC Oscillators 10.3.1 Frequency Calibration 11 OTP Controller 11.1 Introduction 11.2 Architecture 11.2.1 OTP Accessing Considerations 11.3 Programming 12 DMA Controller 12.1 Introduction 12.2 Architecture 12.2.1 DMA Peripherals 12.2.2 Input/Output Multiplexer 12.2.3 DMA Channel Operation 12.2.4 DMA Arbitration 12.2.5 Freezing DMA Channels 12.3 Programming 12.3.1 Memory to Memory Transfers 12.3.2 Peripheral to Memory Transfers 13 I2C Interface 13.1 Introduction 13.2 Architecture 13.2.1 I2C Bus Terms 13.2.1.1 Bus Transfer Terms 13.2.2 I2C Behavior 13.2.2.1 START and STOP Generation 13.2.2.2 Combined Formats 13.2.3 I2C Protocols 13.2.3.1 START and STOP Conditions 13.2.3.2 Addressing Slave Protocol 7-bit Address Format 10-bit Address Format 13.2.3.3 Transmitting and Receiving Protocols Master-Transmitter and Slave-Receiver Master-Receiver and Slave-Transmitter START BYTE Transfer Protocol 13.2.4 Multiple Master Arbitration 13.2.5 Clock Synchronization 13.3 Programming 14 UART 14.1 Introduction 14.2 Architecture 14.2.1 UART (RS232) Serial Protocol 14.2.2 Clock Support 14.2.3 Interrupts 14.2.4 Programmable THRE Interrupt 14.2.5 Shadow Registers 14.2.6 Direct Test Mode 14.3 Programming 15 SPI Interface 15.1 Introduction 15.2 Architecture 15.2.1 SPI Timing 15.3 Programming 15.3.1 Master Mode 15.3.2 Slave Mode 16 Quadrature Decoder 16.1 Introduction 16.2 Architecture 16.3 Programming 17 Clockless Wakeup Controller 17.1 Introduction 17.2 Architecture 17.3 Programming 18 Clocked Wakeup Controller 18.1 Introduction 18.2 Architecture 18.3 Programming 19 Timer 0 19.1 Introduction 19.2 Architecture 19.3 Programming 19.3.1 Timer Functionality 19.3.2 PWM Generation 20 Timer 1 20.1 Introduction 20.2 Architecture 20.3 Programming 20.3.1 Timer Functionality 20.3.2 Capture Functionality 20.3.3 Frequency Measuring Functionality 21 Timer 2 21.1 Introduction 21.2 Architecture 21.3 Programming 21.3.1 PWM Generation 21.3.2 Freeze Functionality 22 Watchdog Timer 22.1 Introduction 22.2 Architecture 22.3 Programming 23 Temperature Sensor 23.1 Introduction 23.2 Architecture 23.2.1 Programming 23.2.1.1 Absolute Temperature 23.2.1.2 Relative Temperature 24 Keyboard Controller 24.1 Introduction 24.2 Architecture 24.2.1 Keyboard Scanner 24.2.2 GPIO Interrupt Generator 24.3 Programming 24.3.1 Keyboard Scanner 24.3.2 GPIO Interrupts 25 Input/Output Ports 25.1 Introduction 25.2 Architecture 25.2.1 Programmable Pin Assignment 25.2.1.1 Priority 25.2.1.2 Direction Control 25.2.2 General Purpose Port Registers 25.2.2.1 Port Data Register 25.2.2.2 Port Set Data Output Register 25.2.2.3 Port Reset Data Output Register 25.2.3 Fixed Assignment Functionality 25.2.4 Types of GPIO Pads 25.2.5 Driving Strength 26 General Purpose ADC 26.1 Introduction 26.2 Architecture 26.2.1 Input Channels 26.2.2 Operating Modes 26.2.2.1 Enabling the ADC 26.2.2.2 Manual Mode 26.2.2.3 Continuous Mode 26.2.3 Conversion Modes 26.2.3.1 AD Conversion Sampling Phase Conversion and Storage Phase 26.2.3.2 Averaging 26.2.3.3 Chopper Mode 26.2.4 Additional Settings 26.2.5 Non-Ideal Effects 26.2.6 Offset Calibration 26.2.7 Zero-Scale Adjustment 26.2.8 Common Mode Adjustment 26.2.9 Input Impedance, Inductance, and Input Settling 26.3 Programming 27 Real Time Clock (RTC) 27.1 Introduction 27.2 Architecture 27.3 Programming 28 Power 28.1 DCDC Converter 28.2 LDOs 28.3 POR Circuit 29 BLE Core 29.1 Architecture 29.1.1 Exchange Memory 29.2 Programming 29.2.1 Wake-Up IRQ 29.2.2 Switch from BLE Active Mode to BLE Deep Sleep Mode 29.2.3 Switch from BLE Deep Sleep Mode to BLE Active Mode 29.2.3.1 Switching at an Anchor Point 29.2.3.2 Switching Due to an External Event 30 Radio 30.1 Introduction 30.2 Architecture 30.2.1 Receiver 30.2.2 Synthesizer 30.2.3 Transmitter 30.2.4 RFIO 30.2.5 Biasing 30.2.6 RF Monitoring 31 Registers 31.1 Analog Miscellaneous Registers 31.2 BLE Core Registers 31.3 Clock Generation and Reset Registers 31.4 DCDC Converter Registers 31.5 DMA Controller Registers 31.6 General Purpose ADC Registers 31.7 General Purpose I/O Registers 31.8 General Purpose Registers 31.9 I2C Interface Registers 31.10 Keyboard Registers 31.11 Miscellaneous Registers 31.12 OTP Controller Registers 31.13 Quadrature Decoder Registers 31.14 Real Time Clock Registers 31.15 SPI Interface Registers 31.16 Timer and Triple PWM Registers 31.17 Timer1 Registers 31.18 UART Interface Registers 31.19 Chip Version Registers 31.20 Wake-Up Registers 31.21 Watchdog Registers 32 Ordering Information 33 Package Information 33.1 Moisture Sensitivity Level (MSL) 33.2 WLCSP Handling 33.3 Soldering Information 33.4 Package Outlines Revision History