Datasheet HMC860LP3E (Analog Devices) - 7
| Hersteller | Analog Devices |
| Beschreibung | Quad Low Noise High PSRR Linear Voltage Regulator |
| Seiten / Seite | 10 / 7 — HMC860LP3E. QUAD LOW NOISE HIGH PSRR. LINEAR VOLTAGE REGULATOR. … |
| Dateiformat / Größe | PDF / 699 Kb |
| Dokumentensprache | Englisch |
HMC860LP3E. QUAD LOW NOISE HIGH PSRR. LINEAR VOLTAGE REGULATOR. Application Schematic. Stability. 9 - 7
Modelllinie für dieses Datenblatt
Textversion des Dokuments
HMC860LP3E
v01.0811
QUAD LOW NOISE HIGH PSRR LINEAR VOLTAGE REGULATOR Application Schematic
9 T M G - S IN N The specified noise performance requires the 1µF decoupling capacitor between pins REF and GND (C1) and the IO 100nF capacitors connected between output VRx (x=1,2,3,4) and the respective RDx pin (C2, C3, C4 and C5). If noise performance is not critical for a particular output, the 100nF capacitor can be omitted for the respective regulator. In IT this case, noise spectral density will typical y increase by a factor of 20X at 10kHz. The 1µF REF capacitor causes a D 25ms typical turn-on start-up time. N O
Stability
R C Two approaches are recommended to manage the stability of the high-current regulators VR1 and VR4. If only one decoupling capacitor is used at the output, the capacitor series resistance Resr must be between 0.2 Ohm and 2 Ohm E to insure stability across all loading conditions. This is shown at output VR4 in the application schematic. Note that W ceramic capacitors typical y have much lower Resr (as low as 0.02 Ohm at resonance) hence they will need a series O resistor to insure stability. P In the case when several capacitors are connected at the output (which is often the case with noise and spurious sensitive circuits), an alternate approach is to insert a small resistor in series with the load but after the 100nF feed- back capacitor. This is shown by Rs1 at the VR1 output in the application schematic. The minimum resistor value is 0.1 Ohm, while the maximum value is set by the acceptable output voltage drop. Due to the lower current, regulators VR2 and VR3 do not have special stability requirements. Typical 10µF ceramic capacitor ESR of 0.02 Ohm is sufficient for their stability. Inf F or o m ra tip o r n ifc ur e n ,is hd e e d lbiv y e A r n y al oa g n D d evi tco e s p is la beclie ev eo d rtd o ebre sa: H ccur iattti e taen M d re ilicarbloew . H a o ve wev eC r, o n r o For price, delivery, and to place orders: Analog Devices, Inc., responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other poration, 2 Elizabeth Drive, Chelmsford, MA 01824 One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
9 - 7
978-250-3343 tel • 978-250-3373 fax • O rights of third parties that may result from its use. Specifications subject to change without notice. No rd P e h r o nO e n : 7 -li 81 n - e 32 a 9- t 4 w 70 ww. 0 • Ohi rd tt e ite r on.lc inom license is granted by implication or otherwise under any patent or patent rights of Analog Devices. e at www.analog.com Application Trademarks and registered trademarks are the property of their respective owners.Support: apps@ A h ppitlitcitae ti .oco n Sm upport: Phone: 1-800-ANALOG-D
v01.0811
QUAD LOW NOISE HIGH PSRR LINEAR VOLTAGE REGULATOR Application Schematic
9 T M G - S IN N The specified noise performance requires the 1µF decoupling capacitor between pins REF and GND (C1) and the IO 100nF capacitors connected between output VRx (x=1,2,3,4) and the respective RDx pin (C2, C3, C4 and C5). If noise performance is not critical for a particular output, the 100nF capacitor can be omitted for the respective regulator. In IT this case, noise spectral density will typical y increase by a factor of 20X at 10kHz. The 1µF REF capacitor causes a D 25ms typical turn-on start-up time. N O
Stability
R C Two approaches are recommended to manage the stability of the high-current regulators VR1 and VR4. If only one decoupling capacitor is used at the output, the capacitor series resistance Resr must be between 0.2 Ohm and 2 Ohm E to insure stability across all loading conditions. This is shown at output VR4 in the application schematic. Note that W ceramic capacitors typical y have much lower Resr (as low as 0.02 Ohm at resonance) hence they will need a series O resistor to insure stability. P In the case when several capacitors are connected at the output (which is often the case with noise and spurious sensitive circuits), an alternate approach is to insert a small resistor in series with the load but after the 100nF feed- back capacitor. This is shown by Rs1 at the VR1 output in the application schematic. The minimum resistor value is 0.1 Ohm, while the maximum value is set by the acceptable output voltage drop. Due to the lower current, regulators VR2 and VR3 do not have special stability requirements. Typical 10µF ceramic capacitor ESR of 0.02 Ohm is sufficient for their stability. Inf F or o m ra tip o r n ifc ur e n ,is hd e e d lbiv y e A r n y al oa g n D d evi tco e s p is la beclie ev eo d rtd o ebre sa: H ccur iattti e taen M d re ilicarbloew . H a o ve wev eC r, o n r o For price, delivery, and to place orders: Analog Devices, Inc., responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other poration, 2 Elizabeth Drive, Chelmsford, MA 01824 One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
9 - 7
978-250-3343 tel • 978-250-3373 fax • O rights of third parties that may result from its use. Specifications subject to change without notice. No rd P e h r o nO e n : 7 -li 81 n - e 32 a 9- t 4 w 70 ww. 0 • Ohi rd tt e ite r on.lc inom license is granted by implication or otherwise under any patent or patent rights of Analog Devices. e at www.analog.com Application Trademarks and registered trademarks are the property of their respective owners.Support: apps@ A h ppitlitcitae ti .oco n Sm upport: Phone: 1-800-ANALOG-D