Datasheet ADP7112 (Analog Devices)

20 V, 200 mA, Low Noise, CMOS LDO Linear Regulator Data Sheet ADP7112 FEATURES TYPICAL APPLICATION CIRCUITS Low noise: 11 μV rms independent of fixed output voltage ADP7112 PSRR of 88 dB at 10 kHz, 68 dB at 100 kHz, 50 dB at 1 MHz, VIN = 6V VOUT = 5V VIN VOUT VOUT = 5 V, VIN = 7 V CIN COUT 2.2µF 2.2µF Input voltage range: 2.7 V to 20 V SENSE/ADJ Maximum output current: 200 mA ON Initial accuracy: ±0.8% EN SS GND C OFF SS
01
Accuracy over line, load, and temperature 1nF
0
±1.8%, T
12508-
J = −40°C to +125°C
Figure 1. ADP7112 with Fixed Output Voltage, 5 V
Low dropout voltage: 200 mV (typical) at a 200 mA load, VOUT = 5 V ADP7112 User-programmable soft start VIN = 7V VOUT = 6V VIN VOUT Low quiescent current, IGND = 50 μA (typical) with no load CIN C 2kΩ OUT Low shutdown current 2.2µF SENSE/ADJ 2.2µF 10kΩ 1.8 μA at VIN = 5 V ON 3.0 μA at V EN SS IN = 20 V GND C OFF SS Stable with a small 2.2 μF ceramic output capacitor 1nF
002
Fixed output voltage options: 1.8 V, 2.5 V, 3.3 V, and 5.0 V
12508- Figure 2. ADP7112 with 5 V Output Adjusted to 6 V
15 standard voltages between 1.2 V and 5.0 V are available Adjustable output from 1.2 V to VIN – VDO, output can be adjusted above initial set point Precision enable 1 mm × 1.2 mm, 6-ball WLCSP APPLICATIONS Regulation to noise sensitive applications ADC and DAC circuits, precision amplifiers, power for VCO VTUNE control Communications and infrastructure Medical and healthcare Industrial and instrumentation GENERAL DESCRIPTION
The ADP7112 is a CMOS, low dropout (LDO) linear regulator The ADP7112 is available in 15 fixed output voltage options. that operates from 2.7 V to 20 V and provides up to 200 mA of The following voltages are available from stock: 1.2 V output current. This high input voltage LDO is ideal for the (adjustable), 1.8 V, 2.5 V, 3.3 V, and 5.0 V. Additional voltages regulation of high performance analog and mixed-signal circuits available by special order are 1.5 V, 1.85 V, 2.0 V, 2.2 V, 2.75 V, operating from 19 V down to 1.2 V rails. Using an advanced 2.8 V, 2.85 V, 3.8 V, 4.2 V, and 4.6 V. proprietary architecture, the device provides high power supply Each fixed output voltage can be adjusted above the initial set rejection, low noise, and achieves excellent line and load transient point with an external feedback divider. This allows the ADP7112 response with a small 2.2 μF ceramic output capacitor. The to provide an output voltage from 1.2 V to VIN − VDO with high ADP7112 regulator output noise is 11 μV rms, independent of PSRR and low noise. the output voltage for the fixed options of 5 V or less. A user-programmable soft start with an external capacitor is available in the ADP7112. The ADP7112 is available in a 6-ball 1 mm × 1.2 mm WLCSP, making it a very compact solution.
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Document Outline Features Applications Typical Application Circuits General Description Revision History Specifications Input and Output Capacitance, Recommended Specifications Absolute Maximum Ratings Thermal Data Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Applications Information Capacitor Selection Output Capacitor Input Bypass Capacitor Input and Output Capacitor Properties Programable Precision Enable Soft Start Noise Reduction of the ADP7112 in Adjustable Mode Current-Limit and Thermal Overload Protection Effect of Noise Reduction on Start-Up Time Thermal Considerations PCB Layout Considerations Outline Dimensions Ordering Guide