Datasheet ADP7157 (Analog Devices) - 6

ADP7157 Data Sheet PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS VOUT 1 10 VIN VOUT 1 8 VIN VOUT 2 9 VIN VOUT_SENSE 2 ADP7157 7 VREG ADP7157 TOP VIEW BYP 3 6 REF VOUT_SENSE 3 8 VREG TOP VIEW (Not to Scale) (Not to Scale) EN 4 5 REF_SENSE BYP 4 7 REF EN 5 6 REF_SENSE NOTES 1. THE EXPOSED PAD IS LOCATED ON THE BOTTOM OF NOTES THE PACKAGE. THE EXPOSED PAD ENHANCES 1. THE EXPOSED PAD IS LOCATED ON THE BOTTOM OF THERMAL PERFORMANCE, AND IT IS ELECTRICALLY
4 0
THE PACKAGE. THE EXPOSED PAD ENHANCES CONNECTED TO GROUND INSIDE THE PACKAGE.
-0 8
THERMAL PERFORMANCE, AND IT IS ELECTRICALLY CONNECT THE EP TO THE GROUND PLANE ON THE
93
CONNECTED TO GROUND INSIDE THE PACKAGE.
03
BOARD TO ENSURE PROPER OPERATION.
12 0
CONNECT THE EP TO THE GROUND PLANE ON THE
8- 93
BOARD TO ENSURE PROPER OPERATION.
12 Figure 3. 10-Lead LFCSP Pin Configuration Figure 4. 8-Lead SOIC Pin Configuration
Table 6. Pin Function Descriptions Pin No. LFCSP SOIC Mnemonic Description
1, 2 1 VOUT Regulated Output Voltage. Bypass VOUT to ground with a 10 μF or greater capacitor. 3 2 VOUT_SENSE Output Sense. VOUT_SENSE is internally connected to VOUT with a 10 Ω resistor. Connect VOUT_SENSE as close to the load as possible. 4 3 BYP Low Noise Bypass Capacitor. Connect a 1 μF or greater capacitor from the BYP pin to ground to reduce noise. Do not connect a load to this pin. 5 4 EN Enable. Drive EN high to turn on the regulator, and drive EN low to turn off the regulator. For automatic startup, connect EN to VIN. 6 5 REF_SENSE Reference Sense. This pin sets the output voltage with an external resistor divider. VOUT = VREF × (R1 + R2)/R2, where VREF = 1.2 V. Connect REF_SENSE to the REF pin. Do not connect REF_SENSE to VOUT or ground. 7 6 REF Low Noise Reference Voltage Output. Bypass REF to ground with a 1 μF or greater capacitor. Short REF_SENSE to REF for fixed output voltages. Do not connect a load to this pin. 8 7 VREG Regulated Input Supply Voltage to the LDO Amplifier. Bypass VREG to ground with a 1 μF or greater capacitor. 9, 10 8 VIN Regulator Input Supply Voltage. Bypass VIN to ground with a 10 μF or greater capacitor. EP Exposed Pad. The exposed pad is located on the bottom of the package. The exposed pad enhances thermal performance, and it is electrically connected to ground inside the package. Connect the exposed pad to the ground plane on the board to ensure proper operation. Rev. B | Page 6 of 23 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TYPICAL APPLICATION CIRCUIT REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL DATA THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION APPLICATIONS INFORMATION ADIsimPOWER DESIGN TOOL CAPACITOR SELECTION Output Capacitor Input and VREG Capacitor REF Capacitor BYP Capacitor Capacitor Properties UNDERVOLTAGE LOCKOUT (UVLO) PROGRAMMABLE PRECISION ENABLE START-UP TIME REF, BYP, AND VREG PINS CURRENT-LIMIT AND THERMAL SHUTDOWN THERMAL CONSIDERATIONS Thermal Characterization Parameter (ΨJB) PSRR PERFORMANCE PCB LAYOUT CONSIDERATIONS OUTLINE DIMENSIONS ORDERING GUIDE