Datasheet ADP1764 (Analog Devices) - 5

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Data Sheet ADP1764 ABSOLUTE MAXIMUM RATINGS Table 4.
ΨJB of the package is based on modeling and calculation using a
Parameter Rating
4-layer board. JESD51-12, Guidelines for Reporting and Using Electronic Package Thermal Information, states that thermal VIN to GND −0.3 V to +2.16 V characterization parameters are not the same as thermal EN to GND −0.3 V to +3.96 V resistances. Ψ VOUT to GND −0.3 V to V JB measures the component power flowing IN through multiple thermal paths rather than a single path as in SENSE to GND −0.3 V to VIN thermal resistance, θ VREG to GND −0.3 V to V JB. Therefore, ΨJB thermal paths include IN convection from the top of the package as wel as radiation from REFCAP to GND −0.3 V to VIN the package, factors that make Ψ VADJ to GND −0.3 V to V JB more useful in real-world IN applications. SS to GND −0.3 V to VIN PG to GND −0.3 V to +3.96 V
THERMAL RESISTANCE/PARAMETER
Storage Temperature Range −65°C to +150°C Values shown in Table 5 are calculated in compliance with Operating Temperature Range −40°C to +125°C JEDEC standards for thermal reporting. θJA is the natural Operating Junction Temperature 125°C convection junction to ambient thermal resistance measured in a Lead Temperature (Soldering, 10 sec) 300°C one cubic foot sealed enclosure. θJC is the junction to case thermal Stresses at or above those listed under Absolute Maximum resistance. θJB is the junction to board thermal resistance. ΨJB is Ratings may cause permanent damage to the product. This is a the junction to board thermal characterization parameter. ΨJT is stress rating only; functional operation of the product at these the junction to top thermal characterization parameter. or any other conditions above those indicated in the operational In applications where high maximum power dissipation exists, section of this specification is not implied. Operation beyond close attention to thermal board design is required. Thermal the maximum operating conditions for extended periods may resistance/parameter values may vary, depending on the PCB affect product reliability. material, layout, and environmental conditions.
THERMAL DATA Table 5. Thermal Resistance/Parameter
Absolute maximum ratings apply individually only, not in
Package
combination. The ADP1764 can be damaged when the junction
Type θJA θJC θJB ΨJB ΨJT Unit
temperature limits are exceeded. The use of appropriate thermal CP-16-481 40.65 7.47 17.38 12.9 0.85 °C/W management techniques is recommended to ensure that the 1 Thermal impedance simulated values are based on a JEDEC 2S2P thermal maximum junction temperature does not exceed the limits shown test board for θJA, θJC, θJB, ΨJB, ΨJT, and a JEDEC 1S0P thermal test board for θJC in Table 4. with four thermal vias. See JEDEC JESD51-12.
ESD CAUTION
Use the fol owing equation to calculate the junction temperature (TJ) from the board temperature (TBOARD) or package top temperature (TTOP): TJ = TBOARD + (PD × ΨJB) TJ = TTOP + (PD × ΨJT) ΨJB is the junction to board thermal characterization parameter and ΨJT is the junction to top thermal characterization parameter with units of °C/W. Rev. A | Page 5 of 20 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TYPICAL APPLICATION CIRCUITS REVISION HISTORY SPECIFICATIONS INPUT AND OUTPUT CAPACITOR: RECOMMENDED SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL DATA THERMAL RESISTANCE/PARAMETER ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION SOFT START FUNCTION ADJUSTABLE OUTPUT VOLTAGE ENABLE FEATURE POWER-GOOD (PG) FEATURE APPLICATIONS INFORMATION CAPACITOR SELECTION Output Capacitor Input Bypass Capacitor Input and Output Capacitor Properties UNDERVOLTAGE LOCKOUT CURRENT-LIMIT AND THERMAL OVERLOAD PROTECTION PARALLELING ADP1764 DEVICES FOR HIGH CURRENT APPLICATIONS THERMAL CONSIDERATIONS PCB LAYOUT CONSIDERATIONS OUTLINE DIMENSIONS ORDERING GUIDE