Datasheet AD8564 (Analog Devices) - 9

AD8564 APPLICATIONS INFORMATION OPTIMIZING HIGH SPEED PERFORMANCE OUTPUT LOADING CONSIDERATIONS
As with any high speed comparator or amplifier, proper design The AD8564 output can deliver up to 40 mA of output current and layout techniques should be used to ensure optimal perform- without any significant increase in propagation delay. The ance from the AD8564. The performance limits of high speed output of the device should not be connected to more than 20 circuitry can easily be a result of stray capacitance, improper TTL input logic gates or drive a load resistance less than 100 Ω. ground impedance, or other layout issues. To ensure the best performance from the AD8564, it is important Minimizing resistance from the source to the input is an important to minimize capacitive loading of the output of the device. consideration in maximizing the high speed operation of the Capacitive loads greater than 50 pF cause ringing on the output AD8564. Source resistance, in combination with equivalent waveform and reduce the operating bandwidth of the comparator. input capacitance, may cause a lagged response at the input, Propagation delay also increases with capacitive loads above 100 pF. thus delaying the output. The input capacitance of the AD8564, in combination with stray capacitance from an input pin to
INPUT STAGE AND BIAS CURRENTS
ground, may result in several picofarads of equivalent capaci- The AD8564 uses a PNP differential input stage that enables the tance. A combination of 3 kΩ source resistance and 5 pF of input common-mode range to extend all the way from the input capacitance yields a time constant of 15 ns, which is slower negative supply rail to within 2.2 V of the positive supply rail. than the 5 ns capability of the AD8564. Source impedances The input common-mode voltage can be found as the average should be less than 1 kΩ for the best performance. of the voltage at the two inputs of the device. To ensure the fastest response time, care should be taken to not allow the It is also important to provide bypass capacitors for the power input common-mode voltage to exceed this voltage. supply in a high speed application. A 1 μF electrolytic bypass capacitor should be placed within 0.5 inches of each power The input bias current for the AD8564 is 4 μA. As with any supply pin to ground. These capacitors reduce any potential PNP differential input stage, this bias current goes to 0 on an voltage ripples from the power supply. In addition, a 10 nF input that is high and doubles on an input that is low. Care should ceramic capacitor should be placed as close as possible to the be taken in choosing resistor values to be connected to the power supply pins to ground. These capacitors act as a charge inputs because large resistors could cause significant voltage reservoir for the device during high frequency switching. drops due to the input bias current. A ground plane is recommended for proper high speed perform- The input capacitance for the AD8564 is typically 3 pF. This can ance. This can be created by using a continuous conductive plane be measured by inserting a large source resistance to the input over the surface of the circuit board, only allowing breaks in the and measuring the change in propagation delay. plane for necessary current paths. The ground plane provides a low inductance ground, eliminating any potential differences at different ground points throughout the circuit board caused from ground bounce. A proper ground plane also minimizes the effects of stray capacitance on the circuit board. Rev. B | Page 9 of 12 Document Outline FEATURES APPLICATIONS PIN CONFIGURATIONS GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION TYPICAL PERFORMANCE CHARACTERISTICS APPLICATIONS INFORMATION OPTIMIZING HIGH SPEED PERFORMANCE OUTPUT LOADING CONSIDERATIONS INPUT STAGE AND BIAS CURRENTS USING HYSTERESIS OUTLINE DIMENSIONS ORDERING GUIDE