Datasheet ADCMP565 (Analog Devices) - 9

ADCMP565 APPLICATION INFORMATION The ADCMP565 comparators are very high speed devices.
CLOCK TIMING RECOVERY
Consequently, high speed design techniques must be employed Comparators are often used in digital systems to recover clock to achieve the best performance. The most critical aspect of any timing signals. High speed square waves transmitted over a ADCMP565 design is the use of a low impedance ground plane. distance, even tens of centimeters, can become distorted due to A ground plane, as part of a multilayer board, is recommended stray capacitance and inductance. Poor layout or improper for proper high speed performance. Using a continuous con- termination can also cause reflections on the transmission line, ductive plane over the surface of the circuit board can create further distorting the signal waveform. A high speed com- this, allowing breaks in the plane only for necessary signal parator can be used to recover the distorted waveform while paths. The ground plane provides a low inductance ground, maintaining a minimum of delay. eliminating any potential differences at different ground points throughout the circuit board caused by ground bounce. A
OPTIMIZING HIGH SPEED PERFORMANCE
proper ground plane also minimizes the effects of stray As with any high speed comparator amplifier, proper design and capacitance on the circuit board. layout techniques should be used to ensure optimal perform- ance from the ADCMP565. The performance limits of high It is also important to provide bypass capacitors for the power speed circuitry can easily be a result of stray capacitance, supply in a high speed application. A 1 µF electrolytic bypass improper ground impedance, or other layout issues. capacitor should be placed within 0.5 inches of each power supply pin to ground. These capacitors will reduce any potential Minimizing resistance from source to the input is an important voltage ripples from the power supply. In addition, a 10 nF consideration in maximizing the high speed operation of the ceramic capacitor should be placed as close as possible from the ADCMP565. Source resistance in combination with equivalent power supply pins on the ADCMP565 to ground. These input capacitance could cause a lagged response at the input, capacitors act as a charge reservoir for the device during high thus delaying the output. The input capacitance of the frequency switching. ADCMP565 in combination with stray capacitance from an input pin to ground could result in several picofarads of The LATCH ENABLE input is active low (latched). If the equivalent capacitance. A combination of 3 kΩ source resistance latching function is not used, the LATCH ENABLE input and 5 pF of input capacitance yields a time constant of 15 ns, should be grounded (ground is an ECL logic high), and the which is significantly slower than the sub 500 ps capability of complementary input, LATCH ENABLE, should be tied to the ADCMP565. Source impedances should be significantly less −2.0 V. This will disable the latching function. than 100 Ω for best performance. Occasionally, one of the two comparator stages within the Sockets should be avoided due to stray capacitance and induc- ADCMP565 will not be used. The inputs of the unused com- tance. If proper high speed techniques are used, the ADCMP565 parator should not be allowed to float. The high internal gain should be free from oscillation when the comparator input may cause the output to oscillate (possibly affecting the signal passes through the switching threshold. comparator that is being used) unless the output is forced into a fixed state. This is easily accomplished by ensuring that the two
COMPARATOR PROPAGATION
inputs are at least one diode drop apart, while also appropriately
DELAY DISPERSION
connecting the LATCH ENABLE and LATCH ENABLE inputs The ADCMP565 has been specifically designed to reduce as described above. propagation delay dispersion over an input overdrive range of 100 mV to 1 V. Propagation delay overdrive dispersion is the The best performance is achieved with the use of proper ECL change in propagation delay that results from a change in the terminations. The open emitter outputs of the ADCMP565 are degree of overdrive (how far the switching point is exceeded by designed to be terminated through 50 Ω resistors to −2.0 V, or the input). The overall result is a higher degree of timing any other equivalent ECL termination. If a −2.0 V supply is not accuracy since the ADCMP565 is far less sensitive to input available, an 82 Ω resistor to ground and a 130 Ω resistor to variations than most comparator designs. −5.2 V provide a suitable equivalent. If high speed ECL signals must be routed more than a centimeter, microstrip or stripline Propagation delay dispersion is a specification that is important techniques may be required to ensure proper transition times in critical timing applications such as ATE, bench instruments, and prevent output ringing. and nuclear instrumentation. Overdrive dispersion is defined Rev. 0 | Page 9 of 16 Document Outline SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL CONSIDERATIONS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TIMING INFORMATION APPLICATION INFORMATION CLOCK TIMING RECOVERY OPTIMIZING HIGH SPEED PERFORMANCE COMPARATOR PROPAGATION DELAY DISPERSION COMPARATOR HYSTERESIS MINIMUM INPUT SLEW RATE REQUIREMENT TYPICAL APPLICATION CIRCUITS TYPICAL PERFORMANCE CHARACTERISTICS OUTLINE DIMENSIONS ORDERING GUIDE