Datasheet ADCMP561, ADCMP562 (Analog Devices) - 6

ADCMP561/ADCMP562 Data Sheet PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS V 1 20 DD VDD QA 1 16 QB QA 2 19 QB QA 2 15 QB QA 3 18 QB V 3 14 GND DD ADCMP561 V 4 ADCMP562 17 DD GND LEA 4 13 LEB TOP VIEW TOP VIEW LEA 5 16 LEB LEA 5 (Not to Scale) (Not to Scale) 12 LEB LEA 6 15 LEB V 6 11 V EE CC V 7 14 EE VCC –INA 7 10 –INB –INA 8 13 –INB +INA 8 9 +INB +INA 9 12 +INB
04687-0-002
HYSA 10 11 HYSB
04687-0-003 Figure 4. ADCMP561 16-Lead QSOP Pin Configuration Figure 5. ADCMP562 20-Lead QSOP Pin Configuration
Table 3. Pin Function Descriptions Pin No. ADCMP561 ADCMP562 Mnemonic Function
1 VDD Logic Supply Terminal. 1 2 QA One of two complementary outputs for Channel A. QA is logic high if the analog voltage at the noninverting input is greater than the analog voltage at the inverting input (provided the comparator is in compare mode). See the description of Pin LEA for more information. 2 3 QA One of two complementary outputs for Channel A. QA is logic low if the analog voltage at the noninverting input is greater than the analog voltage at the inverting input (provided the comparator is in compare mode). See the description of Pin LEA for more information. 3 4 VDD Logic Supply Terminal. 4 5 LEA One of two complementary inputs for Channel A Latch Enable. In compare mode (logic high), the output tracks changes at the input of the comparator. In the latch mode (logic low), the output reflects the input state just prior to the comparator’s being placed in the latch mode. LEA must be driven in conjunction with LEA. If left unconnected, the comparator defaults to compare mode. 5 6 LEA One of two complementary inputs for Channel A Latch Enable. In compare mode (logic low), the output tracks changes at the input of the comparator. In latch mode (logic high), the output reflects the input state just prior to the comparator’s being placed in the latch mode. LEA must be driven in conjunction with LEA. If left unconnected, the comparator defaults to compare mode. 6 7 VEE Negative Supply Terminal. 7 8 −INA Inverting Analog Input of the Differential Input Stage for Channel A. The inverting A input must be driven in conjunction with the noninverting A input. 8 9 +INA Noninverting Analog Input of the Differential Input Stage for Channel A. The noninverting A input must be driven in conjunction with the inverting A input. 10 HYSA Programmable Hysteresis Input. 11 HYSB Programmable Hysteresis Input. 9 12 +INB Noninverting Analog Input of the Differential Input Stage for Channel B. The noninverting B input must be driven in conjunction with the inverting B input. 10 13 −INB Inverting Analog Input of the Differential Input Stage for Channel B. The inverting B input must be driven in conjunction with the noninverting B input. 11 14 VCC Positive Supply Terminal. 12 15 LEB One of two complementary inputs for Channel B Latch Enable. In compare mode (logic low), the output tracks changes at the input of the comparator. In latch mode (logic high), the output reflects the input state just prior to placing the comparator in the latch mode. LEB must be driven in conjunction with LEB. If left unconnected, the comparator defaults to compare mode. Rev. B | Page 6 of 14 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL CONSIDERATIONS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TIMING INFORMATION APPLICATIONS INFORMATION CLOCK TIMING RECOVERY OPTIMIZING HIGH SPEED PERFORMANCE COMPARATOR PROPAGATION DELAY DISPERSION COMPARATOR HYSTERESIS MINIMUM INPUT SLEW RATE REQUIREMENT TYPICAL APPLICATION CIRCUITS OUTLINE DIMENSIONS ORDERING GUIDE