Datasheet ADCMP604, ADCMP605 (Analog Devices) - 9

Data Sheet ADCMP604/ADCMP605 350 0.44 300 +125°C 0.43 250 0.42 V) ) +25°C V S (m 200 G ( 0.41 ESI WIN 0.40 ER 150 T S U YST TP H 0.39 100 OU 0.38 –40°C 50 0.37 0 0.36 0 –2 –4 –6 –8 –10 –12 –14 –16 –18
012
2.4 3.4 4.4 5.4
013
HYS PIN CURRENT (µA)
05916-
VCCO (V)
05916- Figure 11. Hysteresis vs. HYS Pin Current Figure 14. LVDS Output Swing vs. VCCO (V)
3.5 1.425V Q 3.0 s) n ( AY L 2.5 N DE IO AT 2.0 AG P PROPAGATION DELAY RO P 1.5 Q
014
1.0 925.0mV 2.000ns/DIV 0 10 20 30 40 50 60 70 80 90 100
004 05916-
OVERDRIVE (mV)
05916- Figure 12. Propagation Delay vs. Input Overdrive Figure 15. 50 MHz Output Voltage Waveform at VCCO = 2.5 V
1.6 1.543V Q PROPAGATION DELAY RISE ns 1.5 s) n ( AY PROPAGATION L DELAY FALL ns DE 1.4 Q 1.3
015
–0.6 –0.2 0.2 0.6 1.0 1.4 1.8 2.2 2.6 3.0
005
1.043V 2.000ns/DIV
05916-
VCM AT VCC (2.5V)
05916- Figure 13. Propagation Delay vs. Input Common-Mode Voltage Figure 16. 50 MHz Output Voltage Waveform at VCCO = 5 V Rev. C | Page 9 of 14 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ELECTRICAL CHARACTERISTICS TIMING INFORMATION ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS APPLICATIONS INFORMATION POWER/GROUND LAYOUT AND BYPASSING LVDS-COMPATIBLE OUTPUT STAGE USING/DISABLING THE LATCH FEATURE OPTIMIZING PERFORMANCE COMPARATOR PROPAGATION DELAY DISPERSION COMPARATOR HYSTERESIS CROSSOVER BIAS POINTS MINIMUM INPUT SLEW RATE REQUIREMENT TYPICAL APPLICATION CIRCUITS OUTLINE DIMENSIONS ORDERING GUIDE