Datasheet ADCMP604, ADCMP605 (Analog Devices)

Rail-to-Rail, Very Fast, 2.5 V to 5.5 V, Single-Supply LVDS Comparators Data Sheet ADCMP604/ ADCMP605 FEATURES FUNCTIONAL BLOCK DIAGRAM Fully specified rail to rail at V VCCO CCI = 2.5 V to 5.5 V VCCI (ADCMP605 ONLY) Input common-mode voltage from −0.2 V to VCCI + 0.2 V Low glitch LVDS-compatible output stage 1.6 ns propagation delay VP NONINVERTING 37 mW at 2.5 V INPUT Q OUTPUT Shutdown pin ADCMP604/ LVDS ADCMP605 Single-pin control for programmable hysteresis and latch Q OUTPUT VN INVERTING Power supply rejection > 60 dB INPUT −40°C to +125°C operation LE/HYS INPUT
001
(ADCMP605 APPLICATIONS SDN INPUT ONLY)
05916-
High speed instrumentation
Figure 1.
Clock and data signal restoration Logic level shifting or translation Pulse spectroscopy High speed line receivers Threshold detection Peak and zero-crossing detectors High speed trigger circuitry Pulse-width modulators Current-/voltage-controlled oscillators Automatic test equipment (ATE) GENERAL DESCRIPTION
The ADCMP604/ADCMP605 are very fast comparators fabricated A flexible power supply scheme al ows the devices to operate on the Analog Devices, Inc. proprietary XFCB2 process. These with a single 2.5 V positive supply and a −0.5 V to +2.7 V input comparators are exceptional y versatile and easy to use. Features signal range up to a 5.5 V positive supply with a −0.5 V to +5.7 V include an input range from VEE − 0.5 V to VCCI + 0.2 V, low noise, input signal range. Split input/output supplies, with no sequencing LVDS-compatible output drivers, and TTL/CMOS latch inputs restrictions on the ADCMP605, support a wide input signal with adjustable hysteresis and/or shut-down inputs. range with greatly reduced power consumption. The devices offer 1.5 ns propagation delays with 1 ps rms The LVDS-compatible output stage is designed to drive any random jitter (RJ). Overdrive and slew rate dispersion are standard LVDS input. The comparator input stage offers robust typically less than 50 ps. protection against large input overdrive, and the outputs do not phase reverse when the valid input signal range is exceeded. High speed latch and programmable hysteresis features are also provided in a unique single-pin control option. The ADCMP604 is available in a 6-lead SC70 package, and the ADCMP605 is available in a 12-lead LFCSP.
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Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ELECTRICAL CHARACTERISTICS TIMING INFORMATION ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS APPLICATIONS INFORMATION POWER/GROUND LAYOUT AND BYPASSING LVDS-COMPATIBLE OUTPUT STAGE USING/DISABLING THE LATCH FEATURE OPTIMIZING PERFORMANCE COMPARATOR PROPAGATION DELAY DISPERSION COMPARATOR HYSTERESIS CROSSOVER BIAS POINTS MINIMUM INPUT SLEW RATE REQUIREMENT TYPICAL APPLICATION CIRCUITS OUTLINE DIMENSIONS ORDERING GUIDE