Datasheet HMC674LC3C, HMC674LP3E (Analog Devices) - 7

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Data Sheet HMC674LC3C/HMC674LP3E PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS N S N S CCI EE CCI EE V RT HY V V RT HY V 16 15 14 13 16 15 14 13 VTP 1 12 VCCO VTP 1 12 VCCO INP 2 HMC674LC3C 11 Q INP 2 HMC674LP3E 11 Q TOP VIEW TOP VIEW INN 3 (Not to Scale) 10 Q INN 3 (Not to Scale) 10 Q VTN 4 9 VCCO VTN 4 9 VCCO 5 6 7 8 PACKAGE 5 6 7 8 PACKAGE C BASE C BASE CCI LE LE V NI CCI LE LE V NI EE V VEE NOTES NOTES 1. NIC = NOT INTERNALLY CONNECTED. CONNECT 1. NIC = NOT INTERNALLY CONNECTED. CONNECT THIS PIN TO GROUND FOR IMPROVED NOISE.
003
THIS PIN TO GROUND FOR IMPROVED NOISE. 2. EXPOSED PAD. THE EXPOSED PAD MUST BE
004
2. EXPOSED PAD. THE EXPOSED PAD MUST BE CONNECTED TO VEE. CONNECTED TO V
14861-
EE.
14861- Figure 3. HMC674LC3C Pin Configuration Figure 4. HMC674LP3E Pin Configuration
Table 8. HMC674LC3C/ HMC674LP3E Pin Function Descriptions Pin No. Mnemonic Description
1 VTP Termination Resistor Return Pin for VP Input. See Figure 5 for the interface schematic. 2 INP Noninverting Analog Input. See Figure 5 for the interface schematic. 3 INN Inverting Analog Input. See Figure 5 for the interface schematic. 4 VTN Termination Resistor Return Pin for VN Input. See Figure 5 for the interface schematic. 5, 16 VCCI Positive Supply Voltage Input Stage. See Figure 6 for the interface schematic. 6 LE Latch Enable Input Pin, Inverting Side. See the Theory of Operation section for additional information. See Figure 6 for the interface schematic. 7 LE Latch Enable Input Pin, Noninverting Side. See the Theory of Operation section for additional information. See Figure 6 for the interface schematic. 8 NIC Not Internally Connected. Connect this pin to ground for improved noise. 9, 12 VCCO Positive Supply Voltage for the Output Stage. See Figure 7 for the interface schematic. 10 Q Inverting Output. Q is at logic low if the analog voltage at the noninverting input, INP, is greater than the analog voltage at the inverting input, INN, provided that the comparator is in track mode. See the Theory of Operation section for additional information. See Figure 7 for the interface schematic. 11 Q Noninverting Output. Q is at logic high if the analog voltage at the noninverting input, INP, is greater than the analog voltage at the inverting input, INN, provided that the comparator is in track mode. See the Theory of Operation section for additional information. See Figure 7 for the interface schematic. 13 VEE Negative Power Supply, −3 V. See Figure 6 for the interface schematic. 14 HYS Hysteresis Control Pin. Leave this pin disconnected for zero hysteresis. Connect this pin to VEE with a resistor to add the desired amount of hysteresis. See Figure 12 to determine the correct size of the RHYS hysteresis control resistor. See Figure 8 for the interface schematic. 15 RTN Return for ESD Protection. EPAD Exposed Pad. The exposed pad must be connected to VEE. Rev. K | Page 7 of 14 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS LATCH ENABLE (LE/) SPECIFICATIONS DC OUTPUT SPECIFICATIONS AC SPECIFICATIONS POWER SUPPLY SPECIFICATIONS TIMING DESCRIPTIONS Timing Diagram ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS INTERFACE SCHEMATICS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION POWER SEQUENCING APPLICATIONS INFORMATION EVALUATION PRINTED CIRCUIT BOARD (PCB) APPLICATION CIRCUITS OUTLINE DIMENSIONS ORDERING GUIDE