Datasheet AD8465 (Analog Devices)

Rail-to-Rail, Very Fast, 2.5 V to 5.5 V, Single-Supply LVDS Comparator Data Sheet AD8465 FEATURES FUNCTIONAL BLOCK DIAGRAM Fully specified rail to rail at V V V CCI CCO CCI = 2.5 V to 5.5 V Input common-mode voltage from −0.2 V to VCCI + 0.2 V Low glitch LVDS-compatible output stage Propagation delay: 1.6 ns VP NONINVERTING INPUT Q OUTPUT Power dissipation: 37 mW at 2.5 V AD8465 LVDS Shutdown pin Q OUTPUT Single-pin control for programmable hysteresis and latch VN INVERTING INPUT Power supply rejection > 60 dB −40°C to +125°C operation LE/HYS INPUT APPLICATIONS
001
SDN INPUT
07958-
High speed instrumentation
Figure 1.
Clock and data signal restoration Logic level shifting or translation Pulse spectroscopy High speed line receivers Threshold detection Peak and zero-crossing detectors High speed trigger circuitry Pulse-width modulators Current-/voltage-controlled oscillators Automatic test equipment (ATE) Qualified for automotive applications GENERAL DESCRIPTION
The AD8465 is a very fast comparator fabricated on the Analog A flexible power supply scheme al ows the devices to operate Devices, Inc., proprietary XFCB2 process. This comparator is with a single 2.5 V positive supply and a −0.5 V to +2.7 V input exceptional y versatile and easy to use. Features include an signal range up to a 5.5 V positive supply with a −0.5 V to +5.7 V input range from VEE − 0.5 V to VCCI + 0.2 V, low noise, LVDS- input signal range. Split input/output supplies, with no sequencing compatible output drivers, and TTL/CMOS latch inputs with restrictions, support a wide input signal range with greatly adjustable hysteresis and/or shutdown inputs. reduced power consumption. The device offers 1.6 ns propagation delay with 1 ps rms The LVDS-compatible output stage is designed to drive any random jitter (RJ). Overdrive and slew rate dispersion are standard LVDS input. The comparator input stage offers robust typically less than 50 ps. protection against large input overdrive, and the outputs do not phase reverse when the valid input signal range is exceeded. High speed latch and programmable hysteresis features are also provided in a unique single-pin control option. The AD8465 is available in a 12-lead LFCSP.
Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2009–2014 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com
Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ELECTRICAL CHARACTERISTICS TIMING INFORMATION ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS APPLICATION INFORMATION POWER/GROUND LAYOUT AND BYPASSING LVDS-COMPATIBLE OUTPUT STAGE USING/DISABLING THE LATCH FEATURE OPTIMIZING PERFORMANCE COMPARATOR PROPAGATION DELAY DISPERSION COMPARATOR HYSTERESIS CROSSOVER BIAS POINTS MINIMUM INPUT SLEW RATE REQUIREMENT TYPICAL APPLICATION CIRCUITS OUTLINE DIMENSIONS ORDERING GUIDE AUTOMOTIVE PRODUCTS