Datasheet AD8469 (Analog Devices) - 8

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AD8469 Data Sheet APPLICATIONS INFORMATION POWER/GROUND LAYOUT AND BYPASSING VLOGIC
The AD8469 comparator is a high speed device. Despite the low noise output stage, it is essential to use proper high speed
A1 Q1
design techniques to achieve the specified performance. Because comparators are uncompensated amplifiers, feedback in any phase relationship is likely to cause oscillations or undesired
+IN OUTPUT
hysteresis. Of critical importance is the use of low impedance
AV –IN
supply planes, particularly the output supply plane (VCC) and the ground plane. Separate supply planes are recommended as part of a multilayer board. Providing the lowest inductance
A2 Q2
return path for switching currents ensures the best possible performance in the target application. 1 01
GAIN STAGE OUTPUT STAGE
0- It is also important to adequately bypass the input and output 1049 supplies. Place a 0.1 μF bypass capacitor as close as possible to Figure 11. Simplified Schematic Diagram of TTL-/CMOS-Compatible Output Stage each supply pin. The capacitors should be connected to the ground plane with redundant vias placed to provide a physically
OPTIMIZING PERFORMANCE
short return path for output currents flowing back from ground As with any high speed comparator, proper design and layout to the VCC pin. Use high frequency bypass capacitors for mini- techniques are essential to obtain the specified performance. Stray mum inductance and effective series resistance (ESR). Parasitic capacitance, inductance, common power and ground impedances, layout inductance should also be strictly controlled to maximize or other layout issues can severely limit performance and often the effectiveness of the bypass at high frequencies. cause oscillation. Source impedance should be minimized as
TTL-/CMOS-COMPATIBLE OUTPUT STAGE
much as possible. High source impedance, in combination with the parasitic input capacitance of the comparator, causes an unde- To achieve the specified propagation delay performance, keep sirable degradation in bandwidth at the input, therefore degrading the capacitive load at or below the specified maximum value. the overall response. Higher impedances encourage undesired The outputs of the AD8469 are designed to directly drive one coupling. Schottky TTL or three low power Schottky TTL loads (or equivalent). For large fan outputs, buses, or transmission lines,
COMPARATOR PROPAGATION DELAY DISPERSION
use an appropriate buffer to maintain the excellent speed and The AD8469 comparator is designed to reduce propagation delay stability of the comparator. dispersion over a wide input overdrive range of 10 mV to VCC − 1 V. With the rated 15 pF load capacitance applied, more than half Propagation delay dispersion is the variation in propagation delay of the total device propagation delay is output stage slew time. that results from a change in the degree of overdrive or slew rate— For this reason, the total propagation delay decreases as V that is, how far or how fast the input signal exceeds the switching CC decreases, and instability in the power supply may appear as threshold (see Figure 12 and Figure 13). excess delay dispersion. The propagation delay dispersion specification becomes important Delay is measured to the 50% point of the supply that is in use; in high speed, time critical applications, such as data communica- therefore, the fastest times are observed with the V tion, automatic test and measurement, and instrumentation. It is CC supply at 2.5 V, and larger delay values are observed when driving loads also important in event driven applications, such as pulse spectros- that switch at other levels. copy, nuclear instrumentation, and medical imaging. Dispersion is the variation in propagation delay as the input overdrive conditions Overdrive and input slew rate dispersions are not significantly are changed (see Figure 12). affected by output loading and VCC variations. The propagation delay dispersion of the AD8469 is typically <12 ns A simplified schematic diagram of the TTL-/CMOS-compatible as the overdrive varies from 10 mV to 125 mV. This specification output stage is shown in Figure 11. Because of its inherent sym- applies to both positive and negative signals because the device has metry and generally good behavior, this output stage is readily very closely matched delays for both positive-going and negative- adaptable for driving various filters and other unusual loads. going inputs, and very low output skews. Note that for repeatable dispersion measurements the actual device offset is added to the overdrive. Rev. 0 | Page 8 of 12 Document Outline Features Applications General Description Functional Block Diagram Table of Contents Revision History Specifications Electrical Characteristics Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Applications Information Power/Ground Layout and Bypassing TTL-/CMOS-Compatible Output Stage Optimizing Performance Comparator Propagation Delay Dispersion Comparator Hysteresis Crossover Bias Point Minimum Input Slew Rate Requirement Typical Applications Circuits Outline Dimensions Ordering Guide Automotive Products