Datasheet ADCMP551, ADCMP552, ADCMP553 (Analog Devices)

HerstellerAnalog Devices
BeschreibungSingle-Supply, High Speed PECL/LVPECL Comparators
Seiten / Seite15 / 1 — Single-Supply, High Speed. PECL/LVPECL Comparators. Data Sheet. …
RevisionB
Dateiformat / GrößePDF / 204 Kb
DokumentenspracheEnglisch

Single-Supply, High Speed. PECL/LVPECL Comparators. Data Sheet. ADCMP551/. ADCMP552/. ADCMP553. FEATURES. FUNCTIONAL BLOCK DIAGRAM

Datasheet ADCMP551, ADCMP552, ADCMP553 Analog Devices, Revision: B

Modelllinie für dieses Datenblatt

Textversion des Dokuments

Single-Supply, High Speed PECL/LVPECL Comparators Data Sheet ADCMP551/ ADCMP552/ ADCMP553 FEATURES FUNCTIONAL BLOCK DIAGRAM Single power supply HYS* 500 ps propagation delay input to output NONINVERTING Q OUTPUT 125 ps overdrive dispersion INPUT ADCMP551/ Differential PECL/LVPECL compatible outputs ADCMP552/ Differential latch control ADCMP553 INVERTING Q OUTPUT Internal latch pull-up resistors INPUT Power supply rejection greater than 70 dB LATCH ENABLE 700 ps minimum pulse width LATCH ENABLE INPUT INPUT Equivalent input rise time bandwidth > 750 MHz *ADCMP552 ONLY
04722-001
Typical output rise/fall of 500 ps
Figure 1.
Programmable hysteresis GENERAL DESCRIPTION
The ADCMP551/ADCMP552/ADCMP553 are single-supply,
APPLICATIONS
high speed comparators fabricated on Analog Devices, Inc.,
Automatic test equipment
proprietary XFCB process. The devices feature a 500 ps
High speed instrumentation
propagation delay with less than 125 ps overdrive dispersion.
Scope and logic analyzer front ends
Overdrive dispersion, a measure of the difference in propagation
Window comparators
delay under differing overdrive conditions, is a particularly
High speed line receivers
important characteristic of high speed comparators. A separate
Threshold detection
programmable hysteresis pin is available on the ADCMP552.
Peak detection
A differential input stage permits consistent propagation delay
High speed triggers
with a common-mode range from −0.2 V to VCCI − 2.0 V. Outputs
Patient diagnostics
are complementary digital signals and are fully compatible with
Disk drive read channel detection
PECL and 3.3 V LVPECL logic families. The outputs provide
Hand-held test instruments
sufficient drive current to directly drive transmission lines
Zero crossing detectors
terminated in 50 Ω to VCCO − 2 V. A latch input is included
Line receivers and signal restoration
and permits tracking, track-and-hold, or sample-and-hold
Clock drivers
modes of operation. The latch input pins contain internal pull- ups that set the latch in tracking mode when left open. The ADCMP551/ADCMP552/ADCMP553 are specified over the −40°C to +85°C industrial temperature range. The ADCMP551 is available in a 16-lead QSOP package; the ADCMP552 is available in a 20-lead QSOP package; and the ADCMP553 is available in an 8-lead MSOP package.
Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2004–2015 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com
Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL CONSIDERATIONS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TIMING INFORMATION APPLICATIONS INFORMATION CLOCK TIMING RECOVERY OPTIMIZING HIGH SPEED PERFORMANCE COMPARATOR PROPAGATION DELAY DISPERSION COMPARATOR HYSTERESIS MINIMUM INPUT SLEW RATE REQUIREMENT TYPICAL APPLICATION CIRCUITS OUTLINE DIMENSIONS ORDERING GUIDE