Datasheet BM63 (Microchip) - 10
| Hersteller | Microchip |
| Beschreibung | Bluetooth 4.2 Stereo Audio Module |
| Seiten / Seite | 56 / 10 — BM63. TABLE 1-2:. BM63 MODULE PIN DESCRIPTION. Pin No. Pin Type. Name. … |
| Dateiformat / Größe | PDF / 3.6 Mb |
| Dokumentensprache | Englisch |
BM63. TABLE 1-2:. BM63 MODULE PIN DESCRIPTION. Pin No. Pin Type. Name. Description. Preliminary
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BM63
Table 1-2 provides the pin description of the BM63 module.
TABLE 1-2: BM63 MODULE PIN DESCRIPTION Pin No Pin Type Name Description
1 I DR0 I2S interface: digital left/right data 2 I/O RFS0 I2S interface: left/right clock 3 I/O SCLK0 I2S interface: bit clock 4 O DT0 I2S interface: digital left/right data 5 O AOHPR Right-channel, analog headphone output 6 O AOHPM Headphone common mode output/sense input 7 O AOHPL Left-channel, analog headphone output 8 I MIC_N1 MIC1 mono differential analog negative input 9 I MIC_P1 MIC1 mono differential analog positive input 10 P MIC_BIAS Electric microphone biasing voltage 11 I AIR Right-channel, single-ended analog input 12 I AIL Left-channel, single-ended analog input 13 I/O P1_2 EEPROM clock SCL 14 I/O P1_3 EEPROM data SDA 15 I RST_N System Reset (active-low) 16 I/O P0_1 Configurable control or indication pin (Internally pulled-up if configured as an input) • FWD key when Class 2 RF (default), active-low • Class 1 Tx control signal for external RF Tx/Rx switch, active-high 17 I/O P2_4 System configuration pin along with P2_0 and EAN pins used to set the module in any one of these modes: • Application mode (for normal operation) • Test mode (to change EEPROM values) • Write Flash mode (to load a new firmware into the mod- ule), refer to Table 5-1 18 I/O P0_4 Configurable control or indication pin (Internally pulled-up if configured as an input) • NFC detection pin, active-low • Out_Ind_1 19 I/O P1_5 Configurable control or indication pin (Internally pulled-up if configured as an input) • NFC detection pin, active-low • Slide switch detector, active-high • Out_Ind_1 • Multi-SPK Master/Slave mode control (FW dependent) 20 I HCI_RXD HCI-UART data input 21 O HCI_TXD HCI-UART data output 22 P CODEC_VO Power supply/reference voltage for codec. Do not connect, for internal use only 23 P VDD_IO I/O positive supply. Do not connect, for internal use only 24 P ADAP_IN 5V power adapter input DS60001431B-Page 10
Preliminary
2016-2017 Microchip Technology Inc. Document Outline Features DSP Audio Processing FIGURE 1: BM63 MODULE Audio Codec Peripherals RF/Analog HCI Interface MAC/Baseband Processor Operating Condition Compliance Applications Description Table of Contents Most Current Data Sheet Errata Customer Notification System 1.0 Device Overview FIGURE 1-1: Application using BM63 Module FIGURE 1-2: Soundbar and subwoofer applications Using BM63 Module FIGURE 1-3: Soundbar and subwoofer Applications using BM63 MODULE AND smartphone FIGURE 1-4: Multi-speaker application using BM63 MODULE TABLE 1-1: BM63 KEY FEATURES FIGURE 1-5: BM63 Module PIN Diagram TABLE 1-2: BM63 module PIN Description 2.0 Audio 2.1 Digital Signal Processor FIGURE 2-1: Speech Signal Processing FIGURE 2-2: Audio Signal Processing 2.2 Codec FIGURE 2-3: CODEC DAC Dynamic Range FIGURE 2-4: CODEC DAC THD+N versus input power FIGURE 2-5: CODEC DAC FREQUENCY RESPONSE (CAPLESS MODE) FIGURE 2-6: CODEC DAC Frequency response (Single-EndED mode) 2.3 Auxiliary Port 2.4 Analog Speaker Output FIGURE 2-7: ANALOG SPEAKER OUTPUT CAPLESS MODE FIGURE 2-8: ANALOG SPEAKER OUTPUT SINGLE-ENDED MODE 3.0 Transceiver 3.1 Transmitter 3.2 Receiver 3.3 Synthesizer 3.4 Modem 3.5 Adaptive Frequency Hopping (AFH) 4.0 Power Management Unit 4.1 Charging a Battery FIGURE 4-1: BATTERY CHARGING CURVE 4.2 Voltage Monitoring 4.3 LED Driver FIGURE 4-2: LED DRIVER 4.4 Under Voltage Protection 5.0 Application Information 5.1 Host MCU Interface FIGURE 5-1: HOST MCU INTERFACE OVER UART FIGURE 5-2: Power-On/Off Sequence FIGURE 5-3: TIMING SEQUENCE OF RX INDICATION AFTER POWER-ON STATE FIGURE 5-4: TIMING SEQUENCE OF POWER-OFF STATE FIGURE 5-5: TIMING SEQUENCE OF POWER-ON (NACK) FIGURE 5-6: RESET TIMING SEQUENCE IN CASE OF NO RESPONSE FROM MODULE TO HOST MCU 5.2 I2S Mode Application FIGURE 5-7: BM63 MODULE IN I2S MASTER MODE FIGURE 5-8: BM63 MODULE IN I2S SLAVE MODE 5.3 Reset 5.4 External Configuration and Programming FIGURE 5-9: EXTERNAL PROGRAMMING HEADER CONNECTIONS TABLE 5-1: SYSTEM CONFIGURATION I/O PINSETTINGS 5.5 Reference Circuit FIGURE 5-10: BM63 REFERENCE CIRCUIT FOR STEREO HEADSET APPLICATIONS FIGURE 5-11: BM63 REFERENCE CIRCUIT FOR STEREO HEADSET APPLICATIONS FIGURE 5-12: BM63 REFERENCE CIRCUIT FOR STEREO HEADSET APPLICATIONS FIGURE 5-13: BM63 REFERENCE CIRCUIT FOR STEREO HEADSET APPLICATIONS FIGURE 5-14: BM63 REFERENCE CIRCUIT FOR STEREO HEADSET APPLICATIONS 6.0 Printed Antenna Information 6.1 Antenna Radiation Pattern FIGURE 6-1: RECOMMENDED KEEPOUT AREA FOR PCB ANTENNA FIGURE 6-2: PCB ANTENNA 3D RADIATION PATTERN at 2441 MHz TABLE 6-1: BM63 PCB ANTENNA CHARACTERISTICS 6.2 Module Placement Guidelines FIGURE 6-3: BM63 MODULE PLACEMENT GUIDELINES FIGURE 6-4: GND PLANE ON MAIN APPLICATION BOARD 7.0 Physical Dimensions FIGURE 7-1: BM63 module PCB DIMENSIONS FIGURE 7-2: RECOMMENDED BM63 module PCB FOOTPRINT 8.0 Electrical Characteristics 8.1 Absolute Maximum Ratings TABLE 8-1: RECOMMENDED OPERATING CONDITION TABLE 8-2: I/O AND RESET LEVEL TABLE 8-3: BATTERY CHARGER TABLE 8-4: LED DRIVER TABLE 8-5: AUDIO CODEC ANALOG TO DIGITAL CONVERTER TABLE 8-6: AUDIO CODEC DIGITAL TO ANALOG CONVERTER TABLE 8-7: TRANSMITTER SECTION FOR BDR AND EDR TABLE 8-8: RECEIVER SECTION FOR BDR AND EDR TABLE 8-9: BM63 SYSTEM CURRENT CONSUMPTION 8.2 Timing specifications FIGURE 8-1: TIMING DIAGRAM FOR I2S MODES (MASTER/SLAVE) FIGURE 8-2: TIMING DIAGRAM FOR PCM MODES (MASTER/SLAVE) FIGURE 8-3: AUDIO INTERFACE TIMING DIAGRAM TABLE 8-10: AUDIO INTERFACE TIMING Specifications 9.0 Soldering Recommendations FIGURE 9-1: REFLOW PROFILE 10.0 Ordering Information TABLE 10-1: BM63 Module ORDERING INFORMATION Appendix A: Revision History Revision A (June 2016) Revision B (January 2017) TABLE B-1: major Section Updates The Microchip Web Site Customer Change Notification Service Customer Support AMERICAS Corporate Office Atlanta Austin, TX Boston Chicago Dallas Detroit Houston, TX Indianapolis Los Angeles Raleigh, NC New York, NY San Jose, CA Canada - Toronto ASIA/PACIFIC Asia Pacific Office Hong Kong Australia - Sydney China - Beijing China - Chengdu China - Chongqing China - Dongguan China - Guangzhou China - Hangzhou China - Hong Kong SAR China - Nanjing China - Qingdao China - Shanghai China - Shenyang China - Shenzhen China - Wuhan China - Xian ASIA/PACIFIC China - Xiamen China - Zhuhai India - Bangalore India - New Delhi India - Pune Japan - Osaka Japan - Tokyo Korea - Daegu Korea - Seoul Malaysia - Kuala Lumpur Malaysia - Penang Philippines - Manila Singapore Taiwan - Hsin Chu Taiwan - Kaohsiung Taiwan - Taipei Thailand - Bangkok EUROPE Austria - Wels Denmark - Copenhagen Finland - Espoo France - Paris France - Saint Cloud Germany - Garching Germany - Heilbronn Germany - Karlsruhe Germany - Munich Germany - Rosenheim Israel - Ra’anana Italy - Milan Italy - Padova Netherlands - Drunen Norway - Trondheim Spain - Madrid Sweden - Gothenberg UK - Wokingham Table of Contents
BM63
Table 1-2 provides the pin description of the BM63 module.
TABLE 1-2: BM63 MODULE PIN DESCRIPTION Pin No Pin Type Name Description
1 I DR0 I2S interface: digital left/right data 2 I/O RFS0 I2S interface: left/right clock 3 I/O SCLK0 I2S interface: bit clock 4 O DT0 I2S interface: digital left/right data 5 O AOHPR Right-channel, analog headphone output 6 O AOHPM Headphone common mode output/sense input 7 O AOHPL Left-channel, analog headphone output 8 I MIC_N1 MIC1 mono differential analog negative input 9 I MIC_P1 MIC1 mono differential analog positive input 10 P MIC_BIAS Electric microphone biasing voltage 11 I AIR Right-channel, single-ended analog input 12 I AIL Left-channel, single-ended analog input 13 I/O P1_2 EEPROM clock SCL 14 I/O P1_3 EEPROM data SDA 15 I RST_N System Reset (active-low) 16 I/O P0_1 Configurable control or indication pin (Internally pulled-up if configured as an input) • FWD key when Class 2 RF (default), active-low • Class 1 Tx control signal for external RF Tx/Rx switch, active-high 17 I/O P2_4 System configuration pin along with P2_0 and EAN pins used to set the module in any one of these modes: • Application mode (for normal operation) • Test mode (to change EEPROM values) • Write Flash mode (to load a new firmware into the mod- ule), refer to Table 5-1 18 I/O P0_4 Configurable control or indication pin (Internally pulled-up if configured as an input) • NFC detection pin, active-low • Out_Ind_1 19 I/O P1_5 Configurable control or indication pin (Internally pulled-up if configured as an input) • NFC detection pin, active-low • Slide switch detector, active-high • Out_Ind_1 • Multi-SPK Master/Slave mode control (FW dependent) 20 I HCI_RXD HCI-UART data input 21 O HCI_TXD HCI-UART data output 22 P CODEC_VO Power supply/reference voltage for codec. Do not connect, for internal use only 23 P VDD_IO I/O positive supply. Do not connect, for internal use only 24 P ADAP_IN 5V power adapter input DS60001431B-Page 10
Preliminary
2016-2017 Microchip Technology Inc. Document Outline Features DSP Audio Processing FIGURE 1: BM63 MODULE Audio Codec Peripherals RF/Analog HCI Interface MAC/Baseband Processor Operating Condition Compliance Applications Description Table of Contents Most Current Data Sheet Errata Customer Notification System 1.0 Device Overview FIGURE 1-1: Application using BM63 Module FIGURE 1-2: Soundbar and subwoofer applications Using BM63 Module FIGURE 1-3: Soundbar and subwoofer Applications using BM63 MODULE AND smartphone FIGURE 1-4: Multi-speaker application using BM63 MODULE TABLE 1-1: BM63 KEY FEATURES FIGURE 1-5: BM63 Module PIN Diagram TABLE 1-2: BM63 module PIN Description 2.0 Audio 2.1 Digital Signal Processor FIGURE 2-1: Speech Signal Processing FIGURE 2-2: Audio Signal Processing 2.2 Codec FIGURE 2-3: CODEC DAC Dynamic Range FIGURE 2-4: CODEC DAC THD+N versus input power FIGURE 2-5: CODEC DAC FREQUENCY RESPONSE (CAPLESS MODE) FIGURE 2-6: CODEC DAC Frequency response (Single-EndED mode) 2.3 Auxiliary Port 2.4 Analog Speaker Output FIGURE 2-7: ANALOG SPEAKER OUTPUT CAPLESS MODE FIGURE 2-8: ANALOG SPEAKER OUTPUT SINGLE-ENDED MODE 3.0 Transceiver 3.1 Transmitter 3.2 Receiver 3.3 Synthesizer 3.4 Modem 3.5 Adaptive Frequency Hopping (AFH) 4.0 Power Management Unit 4.1 Charging a Battery FIGURE 4-1: BATTERY CHARGING CURVE 4.2 Voltage Monitoring 4.3 LED Driver FIGURE 4-2: LED DRIVER 4.4 Under Voltage Protection 5.0 Application Information 5.1 Host MCU Interface FIGURE 5-1: HOST MCU INTERFACE OVER UART FIGURE 5-2: Power-On/Off Sequence FIGURE 5-3: TIMING SEQUENCE OF RX INDICATION AFTER POWER-ON STATE FIGURE 5-4: TIMING SEQUENCE OF POWER-OFF STATE FIGURE 5-5: TIMING SEQUENCE OF POWER-ON (NACK) FIGURE 5-6: RESET TIMING SEQUENCE IN CASE OF NO RESPONSE FROM MODULE TO HOST MCU 5.2 I2S Mode Application FIGURE 5-7: BM63 MODULE IN I2S MASTER MODE FIGURE 5-8: BM63 MODULE IN I2S SLAVE MODE 5.3 Reset 5.4 External Configuration and Programming FIGURE 5-9: EXTERNAL PROGRAMMING HEADER CONNECTIONS TABLE 5-1: SYSTEM CONFIGURATION I/O PINSETTINGS 5.5 Reference Circuit FIGURE 5-10: BM63 REFERENCE CIRCUIT FOR STEREO HEADSET APPLICATIONS FIGURE 5-11: BM63 REFERENCE CIRCUIT FOR STEREO HEADSET APPLICATIONS FIGURE 5-12: BM63 REFERENCE CIRCUIT FOR STEREO HEADSET APPLICATIONS FIGURE 5-13: BM63 REFERENCE CIRCUIT FOR STEREO HEADSET APPLICATIONS FIGURE 5-14: BM63 REFERENCE CIRCUIT FOR STEREO HEADSET APPLICATIONS 6.0 Printed Antenna Information 6.1 Antenna Radiation Pattern FIGURE 6-1: RECOMMENDED KEEPOUT AREA FOR PCB ANTENNA FIGURE 6-2: PCB ANTENNA 3D RADIATION PATTERN at 2441 MHz TABLE 6-1: BM63 PCB ANTENNA CHARACTERISTICS 6.2 Module Placement Guidelines FIGURE 6-3: BM63 MODULE PLACEMENT GUIDELINES FIGURE 6-4: GND PLANE ON MAIN APPLICATION BOARD 7.0 Physical Dimensions FIGURE 7-1: BM63 module PCB DIMENSIONS FIGURE 7-2: RECOMMENDED BM63 module PCB FOOTPRINT 8.0 Electrical Characteristics 8.1 Absolute Maximum Ratings TABLE 8-1: RECOMMENDED OPERATING CONDITION TABLE 8-2: I/O AND RESET LEVEL TABLE 8-3: BATTERY CHARGER TABLE 8-4: LED DRIVER TABLE 8-5: AUDIO CODEC ANALOG TO DIGITAL CONVERTER TABLE 8-6: AUDIO CODEC DIGITAL TO ANALOG CONVERTER TABLE 8-7: TRANSMITTER SECTION FOR BDR AND EDR TABLE 8-8: RECEIVER SECTION FOR BDR AND EDR TABLE 8-9: BM63 SYSTEM CURRENT CONSUMPTION 8.2 Timing specifications FIGURE 8-1: TIMING DIAGRAM FOR I2S MODES (MASTER/SLAVE) FIGURE 8-2: TIMING DIAGRAM FOR PCM MODES (MASTER/SLAVE) FIGURE 8-3: AUDIO INTERFACE TIMING DIAGRAM TABLE 8-10: AUDIO INTERFACE TIMING Specifications 9.0 Soldering Recommendations FIGURE 9-1: REFLOW PROFILE 10.0 Ordering Information TABLE 10-1: BM63 Module ORDERING INFORMATION Appendix A: Revision History Revision A (June 2016) Revision B (January 2017) TABLE B-1: major Section Updates The Microchip Web Site Customer Change Notification Service Customer Support AMERICAS Corporate Office Atlanta Austin, TX Boston Chicago Dallas Detroit Houston, TX Indianapolis Los Angeles Raleigh, NC New York, NY San Jose, CA Canada - Toronto ASIA/PACIFIC Asia Pacific Office Hong Kong Australia - Sydney China - Beijing China - Chengdu China - Chongqing China - Dongguan China - Guangzhou China - Hangzhou China - Hong Kong SAR China - Nanjing China - Qingdao China - Shanghai China - Shenyang China - Shenzhen China - Wuhan China - Xian ASIA/PACIFIC China - Xiamen China - Zhuhai India - Bangalore India - New Delhi India - Pune Japan - Osaka Japan - Tokyo Korea - Daegu Korea - Seoul Malaysia - Kuala Lumpur Malaysia - Penang Philippines - Manila Singapore Taiwan - Hsin Chu Taiwan - Kaohsiung Taiwan - Taipei Thailand - Bangkok EUROPE Austria - Wels Denmark - Copenhagen Finland - Espoo France - Paris France - Saint Cloud Germany - Garching Germany - Heilbronn Germany - Karlsruhe Germany - Munich Germany - Rosenheim Israel - Ra’anana Italy - Milan Italy - Padova Netherlands - Drunen Norway - Trondheim Spain - Madrid Sweden - Gothenberg UK - Wokingham Table of Contents