Datasheet ADN8833 (Analog Devices) - 8
| Hersteller | Analog Devices |
| Beschreibung | Ultracompact, 1 A Thermoelectric Cooler (TEC) Driver for Digital Control Systems |
| Seiten / Seite | 23 / 8 — ADN8833. Data Sheet. TYPICAL PERFORMANCE CHARACTERISTICS. 100. VIN = … |
| Revision | B |
| Dateiformat / Größe | PDF / 1.6 Mb |
| Dokumentensprache | Englisch |
ADN8833. Data Sheet. TYPICAL PERFORMANCE CHARACTERISTICS. 100. VIN = 3.3V. VIN = 5V. FFIC. LOAD = 2Ω. LOAD = 3Ω. LOAD = 4Ω. LOAD = 5Ω. 0.5. 1.0
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ADN8833 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, unless otherwise noted.
100 100 VIN = 3.3V 90 VIN = 5V 90 80 80 70 70 %) %) ( 60 ( 60 Y Y C C N 50 N 50 IE IE 40 FFIC 40 FFIC E E 30 30 20 20 LOAD = 2Ω LOAD = 3Ω 10 10 LOAD = 4Ω LOAD = 5Ω 0 0
003
0 0.5 1.0 1.5 0 0.5 1.0 1.5
106
TEC CURRENT (A)
12909-
TEC CURRENT (A)
12909- Figure 4. Efficiency vs. TEC Current at VIN = 3.3 V and 5 V in Cooling Mode Figure 7. Efficiency vs. TEC Current at VIN = 3.3 V with Different Loads in with 2 Ω Load Heating Mode
100 VIN = 3.3V V 1.4 90 IN = 5V 80 1.2 A) ( 70 NT 1.0 %) ( 60 Y C 0.8 N 50 C CURRE IE E T 0.6 40 FFIC UM E IM 30 AX 0.4 M 20 LOAD = 2Ω 0.2 LOAD = 3Ω 10 LOAD = 4Ω LOAD = 5Ω 0 0 2.7 3.0 3.5 4.0 4.5 5.0 5.5 0 0.5 1.0 1.5
107 004
INPUT VOLTAGE AT PVIN (V) TEC CURRENT (A)
12909- 12909- Figure 5. Efficiency vs. TEC Current at VIN = 3.3 V and 5 V in Heating Mode Figure 8. Maximum TEC Current vs. Input Voltage at PVIN (VIN = 3.3 V), with 2 Ω Load Without Voltage and Current Limit in Cooling Mode
100 1.4 90 80 1.2 A) ( 70 NT 1.0 (%) 60 0.8 NCY C CURRE 50 E E CI T F 0.6 F 40 UM E IM 30 AX 0.4 M 20 LOAD = 2Ω LOAD = 2Ω 0.2 LOAD = 3Ω LOAD = 3Ω 10 LOAD = 4Ω LOAD = 4Ω LOAD = 5Ω LOAD = 5Ω 0 0 2.7 3.0 3.5 4.0 4.5 5.0 5.5
108 105
0 0.5 1.0 1.5 INPUT VOLTAGE AT PVIN (V) TEC CURRENT (A)
12909- 12909- Figure 6. Efficiency vs. TEC Current at VIN = 3.3 V with Different Loads in Figure 9. Maximum TEC Current vs. Input Voltage at PVIN (VIN = 3.3 V), Cooling Mode Without Voltage and Current Limit in Heating Mode Rev. B | Page 8 of 23 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS DETAILED FUNCTIONAL BLOCK DIAGRAM THEORY OF OPERATION DIGITAL PID CONTROL POWERING THE DRIVER ENABLE AND SHUTDOWN OSCILLATOR CLOCK FREQUENCY External Clock Operation Connecting Multiple ADN8833 Devices SOFT START ON POWER-UP TEC VOLTAGE/CURRENT MONITOR Voltage Monitor Current Monitor MAXIMUM TEC VOLTAGE LIMIT Using a Resistor Divider to Set the TEC Voltage Limit MAXIMUM TEC CURRENT LIMIT Using a Resistor Divider to Set the TEC Current Limit APPLICATIONS INFORMATION TYPICAL APPLICATION WITH DIGITAL PID USING A DAC THERMISTOR SETUP MOSFET DRIVER AMPLIFIERS PWM OUTPUT FILTER REQUIREMENTS Inductor Selection Capacitor Selection INPUT CAPACITOR SELECTION POWER DISSIPATION PWM Regulator Power Dissipation Conduction Loss (PCOND) Switching Loss (PSW) Transition Loss (PTRAN) Linear Regulator Power Dissipation PCB LAYOUT GUIDELINES BLOCK DIAGRAMS AND SIGNAL FLOW GUIDELINES FOR REDUCING NOISE AND MINIMIZING POWER LOSS General PCB Layout Guidelines PWM Power Stage Layout Guidelines Linear Power Stage Layout Guidelines EXAMPLE PCB LAYOUT USING TWO LAYERS OUTLINE DIMENSIONS ORDERING GUIDE
TA = 25°C, unless otherwise noted.
100 100 VIN = 3.3V 90 VIN = 5V 90 80 80 70 70 %) %) ( 60 ( 60 Y Y C C N 50 N 50 IE IE 40 FFIC 40 FFIC E E 30 30 20 20 LOAD = 2Ω LOAD = 3Ω 10 10 LOAD = 4Ω LOAD = 5Ω 0 0
003
0 0.5 1.0 1.5 0 0.5 1.0 1.5
106
TEC CURRENT (A)
12909-
TEC CURRENT (A)
12909- Figure 4. Efficiency vs. TEC Current at VIN = 3.3 V and 5 V in Cooling Mode Figure 7. Efficiency vs. TEC Current at VIN = 3.3 V with Different Loads in with 2 Ω Load Heating Mode
100 VIN = 3.3V V 1.4 90 IN = 5V 80 1.2 A) ( 70 NT 1.0 %) ( 60 Y C 0.8 N 50 C CURRE IE E T 0.6 40 FFIC UM E IM 30 AX 0.4 M 20 LOAD = 2Ω 0.2 LOAD = 3Ω 10 LOAD = 4Ω LOAD = 5Ω 0 0 2.7 3.0 3.5 4.0 4.5 5.0 5.5 0 0.5 1.0 1.5
107 004
INPUT VOLTAGE AT PVIN (V) TEC CURRENT (A)
12909- 12909- Figure 5. Efficiency vs. TEC Current at VIN = 3.3 V and 5 V in Heating Mode Figure 8. Maximum TEC Current vs. Input Voltage at PVIN (VIN = 3.3 V), with 2 Ω Load Without Voltage and Current Limit in Cooling Mode
100 1.4 90 80 1.2 A) ( 70 NT 1.0 (%) 60 0.8 NCY C CURRE 50 E E CI T F 0.6 F 40 UM E IM 30 AX 0.4 M 20 LOAD = 2Ω LOAD = 2Ω 0.2 LOAD = 3Ω LOAD = 3Ω 10 LOAD = 4Ω LOAD = 4Ω LOAD = 5Ω LOAD = 5Ω 0 0 2.7 3.0 3.5 4.0 4.5 5.0 5.5
108 105
0 0.5 1.0 1.5 INPUT VOLTAGE AT PVIN (V) TEC CURRENT (A)
12909- 12909- Figure 6. Efficiency vs. TEC Current at VIN = 3.3 V with Different Loads in Figure 9. Maximum TEC Current vs. Input Voltage at PVIN (VIN = 3.3 V), Cooling Mode Without Voltage and Current Limit in Heating Mode Rev. B | Page 8 of 23 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS DETAILED FUNCTIONAL BLOCK DIAGRAM THEORY OF OPERATION DIGITAL PID CONTROL POWERING THE DRIVER ENABLE AND SHUTDOWN OSCILLATOR CLOCK FREQUENCY External Clock Operation Connecting Multiple ADN8833 Devices SOFT START ON POWER-UP TEC VOLTAGE/CURRENT MONITOR Voltage Monitor Current Monitor MAXIMUM TEC VOLTAGE LIMIT Using a Resistor Divider to Set the TEC Voltage Limit MAXIMUM TEC CURRENT LIMIT Using a Resistor Divider to Set the TEC Current Limit APPLICATIONS INFORMATION TYPICAL APPLICATION WITH DIGITAL PID USING A DAC THERMISTOR SETUP MOSFET DRIVER AMPLIFIERS PWM OUTPUT FILTER REQUIREMENTS Inductor Selection Capacitor Selection INPUT CAPACITOR SELECTION POWER DISSIPATION PWM Regulator Power Dissipation Conduction Loss (PCOND) Switching Loss (PSW) Transition Loss (PTRAN) Linear Regulator Power Dissipation PCB LAYOUT GUIDELINES BLOCK DIAGRAMS AND SIGNAL FLOW GUIDELINES FOR REDUCING NOISE AND MINIMIZING POWER LOSS General PCB Layout Guidelines PWM Power Stage Layout Guidelines Linear Power Stage Layout Guidelines EXAMPLE PCB LAYOUT USING TWO LAYERS OUTLINE DIMENSIONS ORDERING GUIDE