Datasheet ADN8833 (Analog Devices) - 3

Data Sheet ADN8833 SPECIFICATIONS
VIN = 2.7 V to 5.5 V, TJ = −40°C to +125°C for minimum/maximum specifications, and TA =25°C for typical specifications, unless otherwise noted.
Table 2. Parameter Symbol Test Conditions/Comments Min Typ Max Unit
POWER SUPPLY Driver Supply Voltage VPVIN WLCSP 2.7 5.5 V VPVINL, VPVINS LFCSP 2.7 5.5 V Controller Supply Voltage VVDD 2.7 5.5 V Supply Current IVDD PWM not switching 2.1 3.5 mA Shutdown Current ISD EN/SY = AGND or VLIM/SD = AGND 350 700 µA Undervoltage Lockout (UVLO) VUVLO VVDD rising 2.45 2.55 2.65 V UVLO Hysteresis UVLOHYST 80 90 100 mV REFERENCE VOLTAGE VVREF IVREF = 0 mA to 10 mA 2.475 2.50 2.525 V LINEAR OUTPUT Output Voltage VLDR ILDR = 0 A Low 0 V High VPVIN V Maximum Source Current ILDR_SOURCE TJ = −40°C to +125°C 1.0 A Maximum Sink Current ILDR_SINK TJ = −40°C to +125°C 1.0 A On Resistance ILDR = 0.6 A P-MOSFET RDS_PL(ON) WLCSP, VPVIN = 5.0 V 35 50 mΩ WLCSP, VPVIN = 3.3 V 44 60 mΩ LFCSP, VPVIN = 5.0 V 50 65 mΩ LFCSP, VPVIN = 3.3 V 55 75 mΩ N-MOSFET RDS_NL(ON) WLCSP, VPVIN = 5.0 V 31 50 mΩ WLCSP, VPVIN = 3.3 V 40 55 mΩ LFCSP, VPVIN = 5.0 V 45 70 mΩ LFCSP, VPVIN = 3.3 V 50 80 mΩ Leakage Current P-MOSFET ILDR_P_LKG 0.1 10 µA N-MOSFET ILDR_N_LKG 0.1 10 µA Linear Amplifier Gain ALDR 40 V/V LDR Short-Circuit Threshold ILDR_SH_GNDL LDR short to PGNDL, enter hiccup 2.2 A ILDR_SH_PVIN LDR short to PVIN, enter hiccup −2.2 A Hiccup Cycle THICCUP 15 ms PWM OUTPUT Output Voltage VSFB ISFB = 0 A Low 0.06 × VPVIN V High 0.93 × VPVIN V Maximum Source Current ISW_SOURCE TJ = −40°C to +125°C 1.0 A Maximum Sink Current ISW_SINK TJ = −40°C to +125°C 1.0 A On Resistance ISW = 0.6 A P-MOSFET RDS_PS(ON) WLCSP, VPVIN = 5.0 V 47 65 mΩ WLCSP, VPVIN = 3.3 V 60 80 mΩ LFCSP, VPVIN = 5.0 V 60 80 mΩ LFCSP, VPVIN = 3.3 V 70 95 mΩ N-MOSFET RDS_NS(ON) WLCSP, VPVIN = 5.0 V 40 60 mΩ WLCSP, VPVIN = 3.3 V 45 65 mΩ LFCSP, VPVIN = 5.0 V 45 75 mΩ LFCSP, VPVIN = 3.3 V 55 85 mΩ Rev. B | Page 3 of 23 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS DETAILED FUNCTIONAL BLOCK DIAGRAM THEORY OF OPERATION DIGITAL PID CONTROL POWERING THE DRIVER ENABLE AND SHUTDOWN OSCILLATOR CLOCK FREQUENCY External Clock Operation Connecting Multiple ADN8833 Devices SOFT START ON POWER-UP TEC VOLTAGE/CURRENT MONITOR Voltage Monitor Current Monitor MAXIMUM TEC VOLTAGE LIMIT Using a Resistor Divider to Set the TEC Voltage Limit MAXIMUM TEC CURRENT LIMIT Using a Resistor Divider to Set the TEC Current Limit APPLICATIONS INFORMATION TYPICAL APPLICATION WITH DIGITAL PID USING A DAC THERMISTOR SETUP MOSFET DRIVER AMPLIFIERS PWM OUTPUT FILTER REQUIREMENTS Inductor Selection Capacitor Selection INPUT CAPACITOR SELECTION POWER DISSIPATION PWM Regulator Power Dissipation Conduction Loss (PCOND) Switching Loss (PSW) Transition Loss (PTRAN) Linear Regulator Power Dissipation PCB LAYOUT GUIDELINES BLOCK DIAGRAMS AND SIGNAL FLOW GUIDELINES FOR REDUCING NOISE AND MINIMIZING POWER LOSS General PCB Layout Guidelines PWM Power Stage Layout Guidelines Linear Power Stage Layout Guidelines EXAMPLE PCB LAYOUT USING TWO LAYERS OUTLINE DIMENSIONS ORDERING GUIDE