Datasheet ADN8834 (Analog Devices) - 6

ADN8834 Data Sheet ABSOLUTE MAXIMUM RATINGS
Stresses at or above those listed under Absolute Maximum
Table 3.
Ratings may cause permanent damage to the product. This is a
Parameter Rating
stress rating only; functional operation of the product at these PVIN to PGNDL (WLCSP) −0.3 V to +5.75 V or any other conditions above those indicated in the operational PVIN to PGNDS (WLCSP) −0.3 V to +5.75 V section of this specification is not implied. Operation beyond PVINL to PGNDL (LFCSP) −0.3 V to +5.75 V the maximum operating conditions for extended periods may PVINS to PGNDS (LFCSP) −0.3 V to +5.75 V affect product reliability. LDR to PGNDL (WLCSP) −0.3 V to V PVIN
THERMAL RESISTANCE
LDR to PGNDL (LFCSP) −0.3 V to V PVINL SW to PGNDS −0.3 V to +5.75 V θJA is specified for the worst-case conditions, that is, a device SFB to AGND −0.3 V to V soldered in a circuit board for surface-mount packages, and is VDD AGND to PGNDL −0.3 V to +0.3 V based on a 4-layer standard JEDEC board. AGND to PGNDS −0.3 V to +0.3 V
Table 4.
VLIM/SD to AGND −0.3 V to V VDD ILIM to AGND −0.3 V to V
Package Type θ θ Unit JA JC
VDD VREF to AGND −0.3 V to +3 V 25-Ball WLCSP 48 0.6 °C/W VDD to AGND −0.3 V to +5.75 V 24-Lead LFCSP 37 1.65 °C/W IN1P to AGND −0.3 V to V VDD IN1N to AGND −0.3 V to V VDD
ESD CAUTION
OUT1 to AGND −0.3 V to +5.75 V IN2P to AGND −0.3 V to V VDD IN2N to AGND −0.3 V to V VDD OUT2 to AGND −0.3 V to +5.75 V EN/SY to AGND −0.3 V to V VDD ITEC to AGND −0.3 V to +5.75 V VTEC to AGND −0.3 V to +5.75 V Maximum Current VREF to AGND 20 mA OUT1 to AGND 50 mA OUT2 to AGND 50 mA ITEC to AGND 50 mA VTEC to AGND 50 mA Junction Temperature 125°C Storage Temperature Range −65°C to +150°C Lead Temperature (Soldering, 10 sec) 260°C Rev. B | Page 6 of 27 Document Outline Features Applications Functional Block Diagram General Description Revision History Specifications Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Detailed Functional Block Diagram Theory of Operation Analog PID Control Digital PID Control Powering the Controller Enable and Shutdown Oscillator Clock Frequency External Clock Operation Connecting Multiple ADN8834 Devices Temperature Lock Indicator (LFCSP Only) Soft Start on Power-Up TEC Voltage/Current Monitor Voltage Monitor Current Monitor Maximum TEC Voltage Limit Using a Resistor Divider to Set the TEC Voltage Limit Maximum TEC Current Limit Using a Resistor Divider to Set the TEC Current Limit Applications Information Signal Flow Thermistor Setup Thermistor Amplifier (Chopper 1) PID Compensation Amplifier (Chopper 2) MOSFET Driver Amplifiers PWM Output Filter Requirements Inductor Selection Capacitor Selection Input Capacitor Selection Power Dissipation PWM Regulator Power Dissipation Conduction Loss (PCOND) Switching Loss (PSW) Transition Loss (PTRAN) Linear Regulator Power Dissipation PCB Layout Guidelines Block Diagrams and Signal Flow Guidelines for Reducing Noise and Minimizing Power Loss General PCB Layout Guidelines PWM Power Stage Layout Guidelines Linear Power Stage Layout Guidelines Placing the Thermistor Amplifier and PID Components Example PCB Layout Using Two Layers Outline Dimensions Ordering Guide