Datasheet ADN8834 (Analog Devices) - 4

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ADN8834 Data Sheet Parameter Symbol Test Conditions/Comments Min Typ Max Unit
N-MOSFET R WLCSP, V = 5.0 V 40 60 mΩ DS_NS(ON) PVIN WLCSP, V = 3.3 V 45 65 mΩ PVIN LFCSP, V = 5.0 V 45 75 mΩ PVIN LFCSP, V = 3.3 V 55 85 mΩ PVIN Leakage Current P-MOSFET I 0.1 10 µA SW_P_LKG N-MOSFET I 0.1 10 µA SW_N_LKG SW Node Rise Time1 t C = 1 nF 1 ns SW_R SW PWM Duty Cycle2 D 6 93 % SW SFB Input Bias Current I 1 2 µA SFB PWM OSCILLATOR Internal Oscillator Frequency f EN/SY high 1.85 2.0 2.15 MHz OSC EN/SY Input Voltage Low V 0.8 V EN/SY_ILOW High V 2.1 V EN/SY_IHIGH External Synchronization Frequency f 1.85 3.25 MHz SYNC Synchronization Pulse Duty Cycle D 10 90 % SYNC EN/SY Rising to PWM Rising Delay t 50 ns SYNC_PWM EN/SY to PWM Lock Time t Number of SYNC cycles 10 Cycles SY_LOCK EN/SY Input Current I 0.3 0.5 µA EN/SY Pull-Down Current 0.3 0.5 µA ERROR/COMPENSATION AMPLIFIERS Input Offset Voltage V V = 1.5 V, V = V − V 10 100 µV OS1 CM1 OS1 IN1P IN1N V V = 1.5 V, V = V − V 10 100 µV OS2 CM2 OS2 IN2P IN2N Input Voltage Range V , V 0 V V CM1 CM2 VDD Common-Mode Rejection Ratio (CMRR) CMRR , CMRR V , V = 0.2 V to V − 0.2 V 120 dB 1 2 CM1 CM2 VDD Output Voltage High V , V V OH1 OH2 V − VDD 0.04 Low V , V 10 mV OL1 OL2 Power Supply Rejection Ratio (PSRR) PSRR , PSRR 120 dB 1 2 Output Current I , I Sourcing and sinking 5 mA OUT1 OUT2 Gain Bandwidth Product1 GBW , GBW V ,V = 0.5 V to V − 1 V 2 MHz 1 2 OUT1 OUT2 VDD TEC CURRENT LIMIT ILIM Input Voltage Range Cooling V 1.3 V ILIMC V − VREF 0.2 Heating V 0.2 1.2 V ILIMH Current-Limit Threshold Cooling V V = 0.5 V 1.98 2.0 2.02 V ILIMC_TH ITEC Heating V V = 2 V 0.48 0.5 0.52 V ILIMH_TH ITEC ILIM Input Current Heating I −0.2 +0.2 µA ILIMH Cooling I Sourcing current 37.5 40 42.5 µA ILIMC Cooling to Heating Current Detection I 40 mA COOL_HEAT_TH Threshold TEC VOLTAGE LIMIT Voltage Limit Gain A (V − V )/V 2 V/V VLIM DRL SFB VLIM VLIM/SD Input Voltage Range1 V 0.2 V /2 V VLIM VDD VLIM/SD Input Current Cooling I V < V /2 −0.2 +0.2 µA ILIMC OUT2 VREF Heating I V > V /2, sinking current 8 10 12.2 µA ILIMH OUT2 VREF Rev. B | Page 4 of 27 Document Outline Features Applications Functional Block Diagram General Description Revision History Specifications Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Detailed Functional Block Diagram Theory of Operation Analog PID Control Digital PID Control Powering the Controller Enable and Shutdown Oscillator Clock Frequency External Clock Operation Connecting Multiple ADN8834 Devices Temperature Lock Indicator (LFCSP Only) Soft Start on Power-Up TEC Voltage/Current Monitor Voltage Monitor Current Monitor Maximum TEC Voltage Limit Using a Resistor Divider to Set the TEC Voltage Limit Maximum TEC Current Limit Using a Resistor Divider to Set the TEC Current Limit Applications Information Signal Flow Thermistor Setup Thermistor Amplifier (Chopper 1) PID Compensation Amplifier (Chopper 2) MOSFET Driver Amplifiers PWM Output Filter Requirements Inductor Selection Capacitor Selection Input Capacitor Selection Power Dissipation PWM Regulator Power Dissipation Conduction Loss (PCOND) Switching Loss (PSW) Transition Loss (PTRAN) Linear Regulator Power Dissipation PCB Layout Guidelines Block Diagrams and Signal Flow Guidelines for Reducing Noise and Minimizing Power Loss General PCB Layout Guidelines PWM Power Stage Layout Guidelines Linear Power Stage Layout Guidelines Placing the Thermistor Amplifier and PID Components Example PCB Layout Using Two Layers Outline Dimensions Ordering Guide