Datasheet AD9361 (Analog Devices) - 7

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Data Sheet AD9361 Test Conditions/ Parameter1 Symbol Min Typ Max Unit Comments
DIGITAL DATA TIMING (CMOS), VDD_INTERFACE = 2.5 V DATA_CLK Clock Period tCP 16.276 ns 61.44 MHz DATA_CLK and FB_CLK Pulse tMP 45% of tCP 55% of tCP ns Width TX Data TX_FRAME, P0_D, and P1_D Setup to FB_CLK tSTX 1 ns Hold to FB_CLK tHTX 0 ns DATA_CLK to Data Bus Output tDDRX 0 1.2 ns Delay DATA_CLK to RX_FRAME Delay tDDDV 0 1.0 ns Pulse Width ENABLE tENPW tCP ns TXNRX tTXNRXPW tCP ns FDD independent ENSM mode TXNRX Setup to ENABLE tTXNRXSU 0 ns TDD ENSM mode Bus Turnaround Time Before RX tRPRE 2 × tCP ns TDD mode After RX tRPST 2 × tCP ns TDD mode Capacitive Load 3 pF Capacitive Input 3 pF DIGITAL DATA TIMING (LVDS) DATA_CLK Clock Period tCP 4.069 ns 245.76 MHz DATA_CLK and FB_CLK Pulse tMP 45% of tCP 55% of tCP ns Width TX Data TX_FRAME and TX_D Setup to FB_CLK tSTX 1 ns Hold to FB_CLK tHTX 0 ns DATA_CLK to Data Bus Output tDDRX 0.25 1.25 ns Delay DATA_CLK to RX_FRAME Delay tDDDV 0.25 1.25 ns Pulse Width ENABLE tENPW tCP ns TXNRX tTXNRXPW tCP ns FDD independent ENSM mode TXNRX Setup to ENABLE tTXNRXSU 0 ns TDD ENSM mode Bus Turnaround Time Before RX tRPRE 2 × tCP ns After RX tRPST 2 × tCP ns Capacitive Load 3 pF Capacitive Input 3 pF SUPPLY CHARACTERISTICS 1.3 V Main Supply Voltage 1.267 1.3 1.33 V VDD_INTERFACE Supply Nominal Settings CMOS 1.14 2.625 V LVDS 1.71 2.625 V VDD_INTERFACE Tolerance −5 +5 % Tolerance is applicable to any voltage setting VDD_GPO Supply Nominal 1.3 3.3 V When unused, must be Setting set to 1.3 V VDD_GPO Tolerance −5 +5 % Tolerance is applicable to any voltage setting Current Consumption VDDx, Sleep Mode 180 μA Sum of all input currents VDD_GPO 50 μA No load 1 When referencing a single function of a multifunction pin in the parameters, only the portion of the pin name that is relevant to the specification is listed. For full pin names of multifunction pins, refer to the Pin Configuration and Function Descriptions section. Rev. F | Page 7 of 36 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS CURRENT CONSUMPTION—VDD_INTERFACE CURRENT CONSUMPTION—VDDD1P3_DIG AND VDDAx (COMBINATION OF ALL 1.3 V SUPPLIES) ABSOLUTE MAXIMUM RATINGS REFLOW PROFILE THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS 800 MHz FREQUENCY BAND 2.4 GHz FREQUENCY BAND 5.5 GHz FREQUENCY BAND THEORY OF OPERATION GENERAL RECEIVER TRANSMITTER CLOCK INPUT OPTIONS SYNTHESIZERS RF PLLs BB PLL DIGITAL DATA INTERFACE DATA_CLK Signal FB_CLK Signal RX_FRAME Signal ENABLE STATE MACHINE SPI Control Mode Pin Control Mode SPI INTERFACE CONTROL PINS Control Outputs (CTRL_OUT[7:0]) Control Inputs (CTRL_IN[3:0]) GPO PINS (GPO_3 TO GPO_0) AUXILIARY CONVERTERS AUXADC AUXDAC1 and AUXDAC2 POWERING THE AD9361 PACKAGING AND ORDERING INFORMATION OUTLINE DIMENSIONS ORDERING GUIDE