Datasheet AD9361 (Analog Devices) - 4

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AD9361 Data Sheet Test Conditions/ Parameter1 Symbol Min Typ Max Unit Comments
RECEIVERS, 5.5 GHz Noise Figure NF 3.8 dB Maximum RX gain Third-Order Input Intermodulation IIP3 −17 dBm Maximum RX gain Intercept Point Second-Order Input IIP2 42 dBm Maximum RX gain Intermodulation Intercept Point LO Leakage −95 dBm At RX front-end input Quadrature Gain Error 0.2 % Phase Error 0.2 Degrees Modulation Accuracy (EVM) −37 dB 40 MHz reference clock (doubled internally for RF synthesizer) Input S11 −10 dB RX1A to RX2A Isolation 52 dB RX2A to RX1A Isolation 52 dB TRANSMITTERS—GENERAL Center Frequency 46.875 6000 MHz Power Control Range 90 dB Power Control Resolution 0.25 dB TRANSMITTERS, 800 MHz Output S22 −10 dB Maximum Output Power 8 dBm 1 MHz tone into 50 Ω load Modulation Accuracy (EVM) −40 dB 19.2 MHz reference clock Third-Order Output OIP3 23 dBm Intermodulation Intercept Point Carrier Leakage −50 dBc 0 dB attenuation −32 dBc 40 dB attenuation Noise Floor −157 dBm/Hz 90 MHz offset Isolation TX1 to TX2 50 dB TX2 to TX1 50 dB TRANSMITTERS, 2.4 GHz Output S22 −10 dB Maximum Output Power 7.5 dBm 1 MHz tone into 50 Ω load Modulation Accuracy (EVM) −40 dB 40 MHz reference clock Third-Order Output Intermod- OIP3 19 dBm ulation Intercept Point Carrier Leakage −50 dBc 0 dB attenuation −32 dBc 40 dB attenuation Noise Floor −156 dBm/Hz 90 MHz offset Isolation TX1 to TX2 50 dB TX2 to TX1 50 dB TRANSMITTERS, 5.5 GHz Output S22 −10 dB Maximum Output Power 6.5 dBm 7 MHz tone into 50 Ω load Modulation Accuracy (EVM) −36 dB 40 MHz reference clock (doubled internally for RF synthesizer) Third-Order Output OIP3 17 dBm Intermodulation Intercept Point Carrier Leakage −50 dBc 0 dB attenuation −30 dBc 40 dB attenuation Noise Floor −151.5 dBm/Hz 90 MHz offset Isolation TX1 to TX2 50 dB TX2 to TX1 50 dB Rev. F | Page 4 of 36 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS CURRENT CONSUMPTION—VDD_INTERFACE CURRENT CONSUMPTION—VDDD1P3_DIG AND VDDAx (COMBINATION OF ALL 1.3 V SUPPLIES) ABSOLUTE MAXIMUM RATINGS REFLOW PROFILE THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS 800 MHz FREQUENCY BAND 2.4 GHz FREQUENCY BAND 5.5 GHz FREQUENCY BAND THEORY OF OPERATION GENERAL RECEIVER TRANSMITTER CLOCK INPUT OPTIONS SYNTHESIZERS RF PLLs BB PLL DIGITAL DATA INTERFACE DATA_CLK Signal FB_CLK Signal RX_FRAME Signal ENABLE STATE MACHINE SPI Control Mode Pin Control Mode SPI INTERFACE CONTROL PINS Control Outputs (CTRL_OUT[7:0]) Control Inputs (CTRL_IN[3:0]) GPO PINS (GPO_3 TO GPO_0) AUXILIARY CONVERTERS AUXADC AUXDAC1 and AUXDAC2 POWERING THE AD9361 PACKAGING AND ORDERING INFORMATION OUTLINE DIMENSIONS ORDERING GUIDE